Patents by Inventor Enzo Donze

Enzo Donze has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Accelerating phase change memory writes
    Patent number: 8301977
    Abstract: In a phase change memory, the memory array may be written in relatively small chunks. The writing of data to the array and, particularly, the writing of set data, may be accelerated using a hardware accelerator. The hardware accelerator may include an edge detector which detects a short duration signal pulse to trigger the writing of the set data to a cell. As a result, the writing of data may be accelerated, reducing the time to write in some cases.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: October 30, 2012
    Assignee: STMicroelectronics S.r.l.
    Inventors: Meenatchi Jagasivmani, Anthony Ko, Rich E. Fackenthal, Ferdinando Bedeschi, Enzo Donze, Ravi Gutala
  • Programming bit alterable memories
    Patent number: 8064265
    Abstract: Program failures during programming can be corrected during reading using an error correcting code. This allows an array to pass programming more readily, speeding the operation of the memory and avoiding the need to continually reprogram or to issue an error message that the programming was unsuccessful. This makes the memory more user friendly and robust.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: November 22, 2011
    Assignee: Intel Corporation
    Inventors: Meenatchi Jagasivamani, Richard Fackenthal, Ferdinando Bedeschi, Enzo Donze
  • ACCELERATING PHASE CHANGE MEMORY WRITES
    Publication number: 20100169740
    Abstract: In a phase change memory, the memory array may be written in relatively small chunks. The writing of data to the array and, particularly, the writing of set data, may be accelerated using a hardware accelerator. The hardware accelerator may include an edge detector which detects a short duration signal pulse to trigger the writing of the set data to a cell. As a result, the writing of data may be accelerated, reducing the time to write in some cases.
    Type: Application
    Filed: December 30, 2008
    Publication date: July 1, 2010
    Applicant: STMicroelectronics S.r.I.
    Inventors: Meenatchi Jagasivamani, Anthony Ko, Rich E. Fackenthal, Ferdinando Bedeschi, Enzo Donze, Ravi Gutala
  • Generating reference currents compensated for process variation in non-volatile memories
    Patent number: 7675792
    Abstract: In a current reference generator device, a voltage reference generator stage generates a reference voltage (Vref) and an active element output stage receives the reference voltage (Vref) and outputs a reference current (Iref) as a function of the reference voltage (Vref). A control stage is operatively coupled to the voltage reference generator stage and to the active element output stage and controls a first trimmable parameter (m) associated to the voltage reference generator stage and a second trimmable parameter associated to the active element output stage, so as to compensate for changes in a value of the reference current (Iref) due to manufacturing process deviations.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: March 9, 2010
    Assignee: Intel Corporation
    Inventors: Ferdinando Bedeschi, Claudio Resta, Enzo Donze
  • Programming bit alterable memories
    Publication number: 20090196092
    Abstract: Program failures during programming can be corrected during reading using an error correcting code. This allows an array to pass programming more readily, speeding the operation of the memory and avoiding the need to continually reprogram or to issue an error message that the programming was unsuccessful. This makes the memory more user friendly and robust.
    Type: Application
    Filed: January 31, 2008
    Publication date: August 6, 2009
    Inventors: Meenatchi Jagasivamani, Richard Fackenthal, Ferdinando Bedeschi, Enzo Donze
  • Generating reference currents compensated for process variation in non-volatile memories
    Publication number: 20090080267
    Abstract: In a current reference generator device, a voltage reference generator stage generates a reference voltage (Vref) and an active element output stage receives the reference voltage (Vref) and outputs a reference current (Iref) as a function of the reference voltage (Vref). A control stage is operatively coupled to the voltage reference generator stage and to the active element output stage and controls a first trimmable parameter (m) associated to the voltage reference generator stage and a second trimmable parameter associated to the active element output stage, so as to compensate for changes in a value of the reference current (Iref) due to manufacturing process deviations.
    Type: Application
    Filed: September 26, 2007
    Publication date: March 26, 2009
    Inventors: Ferdinando Bedeschi, Claudio Resta, Enzo Donze