Patents by Inventor Enzo M. Donze

Enzo M. Donze has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Interleaved array architecture
    Patent number: 8934291
    Abstract: A partition may be made up of two planes of memory cells in a phase change memory. These planes may be configured so that they are not adjacent to one another. In some embodiments, this may mean that the adjacent planes may share sensing circuits, reducing the overall size of the memory array. In addition, by using non-adjacent planes to make up a partition, the planes may be spaced in a way which reduces resistance of power conveying lines. This may mean that smaller sized lines may be used, further reducing the size of the overall array.
    Type: Grant
    Filed: September 17, 2007
    Date of Patent: January 13, 2015
    Assignee: Intel Corporation
    Inventors: Richard E. Fackenthal, Ferdinando Bedeschi, Meenatchi Jagasivamani, Enzo M. Donze
  • Adaptive wordline programming bias of a phase change memory
    Patent number: 8570795
    Abstract: The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused to match the bitline voltage of the programmed cell.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: October 29, 2013
    Assignee: Intel Corporation
    Inventors: Richard E. Fackenthal, Ferdinando Bedeschi, Meenatchi Jagasivamani, Ravi Annavajjhala, Enzo M. Donze
  • Adaptive Wordline Programming Bias of a Phase Change Memory
    Publication number: 20120268984
    Abstract: The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused to match the bitline voltage of the programmed cell.
    Type: Application
    Filed: June 28, 2012
    Publication date: October 25, 2012
    Inventors: Richard E. Fackenthal, Ferdinando Bedeschi, Meenatchi Jagasivamani, Ravi Annavajjhala, Enzo M. Donze
  • Adaptive wordline programming bias of a phase change memory
    Patent number: 8228723
    Abstract: The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused to match the bitline voltage of the programmed cell.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: July 24, 2012
    Assignee: Intel Corporation
    Inventors: Richard E. Fackenthal, Ferdinando Bedeschi, Meenatchi Jagasivamani, Ravi Annavajjhala, Enzo M. Donze
  • Adaptive Wordline Programming Bias of a Phase Change Memory
    Publication number: 20110292721
    Abstract: The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused to match the bitline voltage of the programmed cell.
    Type: Application
    Filed: August 8, 2011
    Publication date: December 1, 2011
    Inventors: Richard E. Fackenthal, Ferdinando Bedeschi, Meenatchi Jagasivamani, Ravi Annavajjhala, Enzo M. Donze
  • Adaptive wordline programming bias of a phase change memory
    Patent number: 8018763
    Abstract: The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused to match the bitline voltage of the programmed cell.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: September 13, 2011
    Assignee: Intel Corporation
    Inventors: Richard E. Fackenthal, Ferdinando Bedeschi, Meenatchi Jagasivamani, Ravi Annavajjhala, Enzo M. Donze
  • Adaptive Wordline Programming Bias of a Phase Change Memory
    Publication number: 20110080777
    Abstract: The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused to match the bitline voltage of the programmed cell.
    Type: Application
    Filed: December 9, 2010
    Publication date: April 7, 2011
    Inventors: Richard E. Fackenthal, Ferdinando Bedeschi, Meenatchi Jagasivamani, Ravi Annavajjhala, Enzo M. Donze
  • Adaptive wordline programming bias of a phase change memory
    Patent number: 7885099
    Abstract: The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused to match the bitline voltage of the programmed cell.
    Type: Grant
    Filed: September 18, 2007
    Date of Patent: February 8, 2011
    Assignee: Intel Corporation
    Inventors: Richard E. Fackenthal, Ferdinando Bedeschi, Meenatchi Jagasivamani, Ravi Annavajjhala, Enzo M. Donze
  • Adaptive wordline programming bias of a phase change memory
    Publication number: 20090073752
    Abstract: The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused to match the bitline voltage of the programmed cell.
    Type: Application
    Filed: September 18, 2007
    Publication date: March 19, 2009
    Inventors: Richard E. Fackenthal, Ferdinando Bedeschi, Meenatchi Jagasivamani, Ravi Annavajjhala, Enzo M. Donze
  • Interleaved array architecture
    Publication number: 20090073751
    Abstract: A partition may be made up of two planes of memory cells in a phase change memory. These planes may be configured so that they are not adjacent to one another. In some embodiments, this may mean that the adjacent planes may share sensing circuits, reducing the overall size of the memory array. In addition, by using non-adjacent planes to make up a partition, the planes may be spaced in a way which reduces resistance of power conveying lines. This may mean that smaller sized lines may be used, further reducing the size of the overall array.
    Type: Application
    Filed: September 17, 2007
    Publication date: March 19, 2009
    Inventors: Richard E. Fackenthal, Ferdinando Bedeschi, Meenatchi Jagasivamani, Enzo M. Donze