Abstract: An equalizer with two parallel branches for precursor and postcursor correction, receiving periodically incoming binary pulse samples, generates for each sample two purged symbols f, b at the outputs of these branches along with two decided symbols f and b, all of which are transmitted to a logic network checking whether or not the two decided symbols are identical. In the event of a disparity, the network produces an estimated signal s, calculates the absolute differences d.sub.sf, d.sub.sb between signals s and f, b, supplements them with further signals d.sub.f, d.sub.b representing the contributions of postcursors and precursors from one or more preceding and following samples, and compares resulting discriminatory signals D.sub.f and D.sub.b to determine which of the two decided symbols should be emitted as an output signal of the equalizer.