Abstract: An output driver includes a pull-up circuit and a pull-down circuit coupled to an output terminal and a capacitor having a first terminal coupled to a gate terminal of a P-channel transistor of the pull-up circuit and a second terminal configured to receive a drive signal. The output driver further includes a drive circuit coupled to the first terminal of the capacitor and configured to transfer charge from a power supply node to the first terminal of the capacitor when the drive signal is at a signal ground voltage and to decouple the first terminal of the capacitor from the power supply node when the drive signal is at a voltage level greater than the signal ground voltage such that a voltage swing of a signal generated at the gate terminal of the P-channel transistor is constrained to be less than a voltage of the power supply node with respect to the signal ground voltage.

Abstract: An output driver includes a pull-up circuit and a pull-down circuit coupled to an output terminal and a capacitor having a first terminal coupled to a gate terminal of a P-channel transistor of the pull-up circuit and a second terminal configured to receive a drive signal. The output driver further includes a drive circuit coupled to the first terminal of the capacitor and configured to transfer charge from a power supply node to the first terminal of the capacitor when the drive signal is at a signal ground voltage and to decouple the first terminal of the capacitor from the power supply node when the drive signal is at a voltage level greater than the signal ground voltage such that a voltage swing of a signal generated at the gate terminal of the P-channel transistor is constrained to be less than a voltage of the power supply node with respect to the signal ground voltage.

Abstract: A semiconductor IC device includes at least one IO port, a core logic, and at least one fail-safe IO circuit, the fail-safe IO circuit being coupled between the core logic and the IO port, wherein the fail-safe IO circuit is configured to receive a predetermined control signal and to maintain the IO port at a predetermined impedance with respect to the predetermined control signal.

Abstract: A bus holder includes a first inverter, a second inverter and a pass switch. The first inverter is coupled between a first power supply voltage node and a second power supply voltage node, and receives an input signal via an input terminal to output a first output signal having an inverted phase with respect to the input signal. The second inverter is coupled between the first power supply voltage node and the second power supply voltage node, and inverts the first output signal to output a second output signal, having an inverted phase with respect to the first output signal, to an output terminal. The pass switch is coupled between the input terminal and the output terminal, and outputs a signal having a level of a control voltage to the input terminal, in response to the control voltage. Accordingly, a tolerant input/output buffer may stably maintain an input signal level when a bus is floated.

Abstract: An input circuit includes an input signal transmission circuit configured to output a first transmission signal at a first output node in response to an input signal at an input node, and a Schmitt trigger inverter configured to output a second transmission signal at a second output node in response to the first transmission signal. The input signal transmission circuit includes a voltage drop element connected to the input node and configured to provide a voltage drop between the input node and a transistor having a gate to which a first supply voltage is applied.

Abstract: A semiconductor IC device includes at least one IO port, a core logic, and at least one fail-safe IO circuit, the fail-safe IO circuit being coupled between the core logic and the IO port, wherein the fail-safe IO circuit is configured to receive a predetermined control signal and to maintain the IO port at a predetermined impedance with respect to the predetermined control signal.

Abstract: A bus holder includes a first inverter, a second inverter and a pass switch. The first inverter is coupled between a first power supply voltage node and a second power supply voltage node, and receives an input signal via an input terminal to output a first output signal having an inverted phase with respect to the input signal. The second inverter is coupled between the first power supply voltage node and the second power supply voltage node, and inverts the first output signal to output a second output signal, having an inverted phase with respect to the first output signal, to an output terminal. The pass switch is coupled between the input terminal and the output terminal, and outputs a signal having a level of a control voltage to the input terminal, in response to the control voltage. Accordingly, a tolerant input/output buffer may stably maintain an input signal level when a bus is floated.

Abstract: An input circuit includes an input signal transmission circuit configured to output a first transmission signal at a first output node in response to an input signal at an input node, and a Schmitt trigger inverter configured to output a second transmission signal at a second output node in response to the first transmission signal. The input signal transmission circuit includes a voltage drop element connected to the input node and configured to provide a voltage drop between the input node and a transistor having a gate to which a first supply voltage is applied.