Abstract: Embodiments of the disclosure provide an electrically programmable fuse (efuse) over crystalline semiconductor material. A structure according to the disclosure includes a plurality of crystalline semiconductor layers. Each crystalline semiconductor layer includes a compound material. A metallic layer is on the plurality of crystalline semiconductor layers. The metallic layer has a lower resistivity than an uppermost layer of the plurality of crystalline semiconductor layers. A pair of gate conductors is on respective portions of the metallic layer. The metallic layer defines an electrically programmable fuse (efuse) link between the gate conductors.

Abstract: Embodiments of the disclosure provide a circuit structure including an electrically programmable fuse (efuse) and lateral bipolar transistor. A structure of the disclosure includes a lateral bipolar transistor within a semiconductor layer and over a substrate. An insulator layer is over a portion of the semiconductor layer. An efuse structure is within a polycrystalline semiconductor layer and over the insulator layer. The efuse structure is over a current path through the lateral bipolar transistor.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an eFuse and gate structure on a triple-well and methods of manufacture. The structure includes: a substrate comprising a bounded region; a gate structure formed within the bounded region; and an eFuse formed within the bounded region and electrically connected to the gate structure.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an eFuse and gate structure on a triple-well and methods of manufacture. The structure includes: a substrate comprising a bounded region; a gate structure formed within the bounded region; and an eFuse formed within the bounded region and electrically connected to the gate structure.

Abstract: An electrical fuse (e-fuse) includes a fuse link including a silicided semiconductor layer over a dielectric layer covering a gate conductor. The silicided semiconductor layer is non-planar and extends orthogonally over the gate conductor. A first terminal is electrically coupled to a first end of the fuse link, and a second terminal is electrically coupled to a second end of the fuse link. The fuse link may be formed in the same layer as an intrinsic and/or extrinsic base of a bipolar transistor. The gate conductor may control a current source for programming the e-fuse. The e-fuse reduces the footprint and the required programming energy compared to conventional e-fuses.

Abstract: An electrical fuse (e-fuse) includes a fuse link including a silicided semiconductor layer over a dielectric layer covering a gate conductor. The silicided semiconductor layer is non-planar and extends orthogonally over the gate conductor. A first terminal is electrically coupled to a first end of the fuse link, and a second terminal is electrically coupled to a second end of the fuse link. The fuse link may be formed in the same layer as an intrinsic and/or extrinsic base of a bipolar transistor. The gate conductor may control a current source for programming the e-fuse. The e-fuse reduces the footprint and the required programming energy compared to conventional e-fuses.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electronic fuse (e-fuse) cells integrated with a bipolar device and methods of manufacture. The structure includes: a bipolar device comprising a collector region, a base region and an emitter region; and an e-fuse integrated with and extending from the emitter region of the bipolar device.

Abstract: The present disclosure relates to an electrostatic discharge (ESD) clamp and, more particularly, to an ESD clamp with reduced off-state power consumption. The structure includes: one or more inverters connected to a timing circuit; a first transistor receiving an output signal from a last of the one or more inverters and an output signal from the timing circuit; a second transistor with its gate connected to the first transistor, in series; and a voltage node providing a separate voltage to a gate of the second transistor.

Abstract: The disclosure provides an apparatus for preventing an integrated circuit (IC) structure from entering a latch-up mode. In an embodiment, the apparatus may include: a p-type substrate; an n-well within the p-type substrate; an n-type region within the p-type substrate, the n-type region being distinct from the n-well; a p-type region within the n-well; a power supply electrically coupled to the p-type region within the n-well; and a directional diode electrically coupling the power supply to the n-well in parallel with the p-type region. The directional diode biases a current flow from the power supply to the n-well, and the directional diode contacts the n-well distal to the p-type region.

Abstract: The disclosure provides an apparatus for preventing an integrated circuit (IC) structure from entering a latch-up mode. In an embodiment, the apparatus may include: a p-type substrate; an n-well within the p-type substrate; an n-type region within the p-type substrate, the n-type region being distinct from the n-well; a p-type region within the n-well; a power supply electrically coupled to the p-type region within the n-well; and a directional diode electrically coupling the power supply to the n-well in parallel with the p-type region. The directional diode biases a current flow from the power supply to the n-well, and the directional diode contacts the n-well distal to the p-type region.

Abstract: The present disclosure relates to an electrostatic discharge (ESD) clamp and, more particularly, to an ESD clamp with reduced off-state power consumption. The structure includes: one or more inverters connected to a timing circuit; a first transistor receiving an output signal from a last of the one or more inverters and an output signal from the timing circuit; a second transistor with its gate connected to the first transistor, in series; and a voltage node providing a separate voltage to a gate of the second transistor.

Abstract: ESD protection circuitry that includes one, or more, of the following features, characteristics and/or advantages: (i) use of different “diode types” (for example, Schottky type, PN type, p-type diode-connected field-effect transistor (FET) type, NFET type)) in a series-connected diode set (connected in series with respect to a device-under-protection) and a parallel-connected diode set (connected in parallel with respect to a device-under-protection and the series-connected diode set); (ii) a FET is connected in series with a target device such that the FET's gate can be turned on during normal operation and the FET's gate is resistively coupled to the FET's source; and/or (iii) two FETs are connected in series with a target device such both FETs gates can be turned on during normal operation, one FET's gate is resistively coupled to its source, and the other FET's gate is electrically coupled to its drain.

Abstract: ESD protection circuitry that includes one, or more, of the following features, characteristics and/or advantages: (i) use of different “diode types” (for example, Schottky type, PN type, p-type diode-connected field-effect transistor (FET) type, NFET type)) in a series-connected diode set (connected in series with respect to a device-under-protection) and a parallel-connected diode set (connected in parallel with respect to a device-under-protection and the series-connected diode set); (ii) a FET is connected in series with a target device such that the FET's gate can be turned on during normal operation and the FET's gate is resistively coupled to the FET's source; and/or (iii) two FETs are connected in series with a target device such both FETs gates can be turned on during normal operation, one FET's gate is resistively coupled to its source, and the other FET's gate is electrically coupled to its drain.

Abstract: ESD protection circuitry that includes one, or more, of the following features, characteristics and/or advantages: (i) use of different “diode types” (for example, Schottky type, PN type, p-type diode-connected field-effect transistor (FET) type, NFET type)) in a series-connected diode set (connected in series with respect to a device-under-protection) and a parallel-connected diode set (connected in parallel with respect to a device-under-protection and the series-connected diode set); (ii) a FET is connected in series with a target device such that the FET's gate can be turned on during normal operation and the FET's gate is resistively coupled to the FET's source; and/or (iii) two FETs are connected in series with a target device such both FETs gates can be turned on during normal operation, one FET's gate is resistively coupled to its source, and the other FET's gate is electrically coupled to its drain.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge (ESD) protection structures for eFuses. The structure includes an electrostatic discharge (ESD) protection structure operatively coupled to an eFuse, which is structured to prevent unintentional programming of the eFuse due to an ESD event originating at a source.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge (ESD) protection structures for eFuses. The structure includes an electrostatic discharge (ESD) protection structure operatively coupled to an eFuse, which is structured to prevent unintentional programming of the eFuse due to an ESD event originating at a source.

Abstract: A magneto-resistive (MR) sensor protection circuit is disclosed, for the protection of an MR sensor. The MR sensor may have a safe operating voltage range, a normal operating voltage range within the safe operating voltage range, and two terminals coupled to a read channel circuit, including a positive terminal and a negative terminal. The MR sensor protection circuit may have positive and negative protection threshold voltage ranges. The MR sensor protection circuit may also have a plurality of N-channel field-effect transistors (NFETs) that are coupled to the positive terminal and to the negative terminal, and configured to, in response to a voltage between the two terminals being within either the positive or the negative protection threshold voltage range, limit the voltage between the terminals by shunting current between the positive terminal and the negative terminal.

Abstract: A method for matching a pair of matched bipolar transistors in an integrated circuit is disclosed. Within a device, it is determined which transistor is a correctable transistor of the pair of bipolar transistors. The correctable transistor is the transistor of the pair of bipolar transistors having a chosen characteristic which when electrically stressed will converge with a chosen characteristic of the other transistor of the pair of bipolar transistors. The pair of bipolar transistors are matched by electrically stressing the correctable transistor of the bipolar transistors.

Abstract: ESD protection circuitry that includes one, or more, of the following features, characteristics and/or advantages: (i) use of different “diode types” (for example, Schottky type, PN type, p-type diode-connected field-effect transistor (FET) type, NFET type)) in a series-connected diode set (connected in series with respect to a device-under-protection) and a parallel-connected diode set (connected in parallel with respect to a device-under-protection and the series-connected diode set); (ii) a FET is connected in series with a target device such that the FET's gate can be turned on during normal operation and the FET's gate is resistively coupled to the FET's source; and/or (iii) two FETs are connected in series with a target device such both FETs gates can be turned on during normal operation, one FET's gate is resistively coupled to its source, and the other FET's gate is electrically coupled to its drain.

Abstract: A magneto-resistive (MR) sensor protection circuit is disclosed, for the protection of an MR sensor. The MR sensor may have a safe operating voltage range, a normal operating voltage range within the safe operating voltage range, and two terminals coupled to a read channel circuit, including a positive terminal and a negative terminal. The MR sensor protection circuit may have positive and negative protection threshold voltage ranges. The MR sensor protection circuit may also have a plurality of N-channel field-effect transistors (NFETs) that are coupled to the positive terminal and to the negative terminal, and configured to, in response to a voltage between the two terminals being within either the positive or the negative protection threshold voltage range, limit the voltage between the terminals by shunting current between the positive terminal and the negative terminal.