Abstract: Embodiments of this application provide a method and apparatus for wired data transmission. The method is applied at a first end, data transmission is performed between the first end and a second end over a first data link, and the first data link is a serial data link or a parallel data link. The method includes: receiving a second rate range sent by the second end, where the second rate range belongs to a transmission rate range supported when the second end receives data over the first data link; sending a second training bitstream to the second end, where a first rate belongs to the second rate range; and sending the data to the second end at the first rate over the first data link. Embodiments are implemented, to change a transmission rate of a data link in a rate range, and reduce a communication resource waste.

Abstract: This application provides a retimer path control method, apparatus, and system for wired serial data transmission. The method includes: receiving a first bitstream, where the first bitstream includes a first field, the first field includes capability information of a retimer, and the capability information indicates whether the retimer supports a low latency path; and sending a second bitstream to the retimer, where the second bitstream includes a second field, the second field includes first enter control information, the first enter control information indicates whether the retimer enters the low latency path, and the low latency path is a path with lowest latency in data transmission paths of the retimer. In this application, the path of the retimer can be effectively controlled.

Abstract: In accordance with an embodiment, a method includes: generating a bitstream, wherein the bitstream comprises data and a control word, and the control word comprises: a first field indicating start location information of the control word, a second field indicating end location information of the control word, and a third field carrying link information indicating a wired serial link; and sending the bitstream over the wired serial link.

Abstract: A high-speed serial interface includes a physical layer circuit at a transmit end, a monitor, a clock gating circuit, a control bitstream generation circuit, and a random bitstream generation circuit. The monitor is configured to: when no service data is being sent, instruct the clock gating circuit to stop sending a clock signal to partial modules in the physical layer circuit at the transmit end. The control bitstream generation circuit sends a first control bitstream through a serializer/deserializer (SerDes), to indicate that the transmit end has turned off partial modules in the physical layer (PHY) circuit at the transmit end and so on. The random bitstream generation circuit sends a random bitstream.

Abstract: A first apparatus receives a first training sequences block (TSB) sent by a second apparatus, where the first TSB includes second spread spectrum capability information of the second apparatus. The first apparatus determines, based on first spread spectrum capability information of the first apparatus and the second spread spectrum capability information, whether to enable spectrum spreading of the second apparatus. The first apparatus sends a second TSB to the second apparatus, where the second TSB includes first indication information, and the first indication information indicates the second apparatus to enable or not to enable the spectrum spreading.

Abstract: This application provides a spread spectrum clock negotiation method, and a peripheral component interconnect express device and system, to implement dynamic negotiation between a transmit end and a receive end on an SSC capability in the peripheral component interconnect express system. The method includes: A second PCIe device generates first indication information, where the first indication information is used to indicate whether the second PCIe device has a spread spectrum clock capability. The second PCIe device sends the first indication information to a first PCIe device. The first PCIe device determines, based on the first indication information, whether to perform spread spectrum clock on a reference clock of the first PCIe device.

Abstract: A transmitter equalization parameter evaluation method and an apparatus are provided. The method provided in this application is used for evaluating a transmitter equalization parameter of a high-speed interface in a first device, and the method is performed by a second device connected to the first device over a communication link. The second device first detects a status of the communication link between the first device and the second device, where the communication link is constructed through the high-speed interface in the first device. When determining that the communication link is idle, the second device performs a transmitter equalization parameter evaluation process of the high-speed interface in the first device based on the communication link. When the communication link is idle, the transmitter equalization parameter evaluation process of the high-speed interface in the first device is started. This ensures efficiency of transmitter equalization parameter evaluation.

Abstract: This application provides a spread spectrum clock negotiation method, and a peripheral component interconnect express device and system, to implement dynamic negotiation between a transmit end and a receive end on an SSC capability in the peripheral component interconnect express system. The method includes: A second PCIe device generates first indication information, where the first indication information is used to indicate whether the second PCIe device has a spread spectrum clock capability. The second PCIe device sends the first indication information to a first PCIe device. The first PCIe device determines, based on the first indication information, whether to perform spread spectrum clock on a reference clock of the first PCIe device.

Abstract: This application provides a data processing method, a device, and a data transmission system. The method includes: A first device determines a first mode from a plurality of error detection and correction modes based on an obtained first status parameter of a data link. Then, the first device may indicate a second device to use the first mode for encoding, the first device may use the first mode for decoding, thereby implementing error detection and correction of transmitted data. In the method provided in this embodiment of this application, the first device and the second device may support a plurality of error detection and correction modes, and the first device may determine a used error detection and correction mode based on a status parameter of the data link.

Abstract: This application relates to a link width adjustment method and apparatus. The method includes: sending, to a second-end apparatus through a first channel, a first packet indicating to perform link width switching; receiving a second packet that is returned by the second-end apparatus and that indicates that the link width switching is agreed on; sending, to the second-end apparatus through a second channel, a first bit stream to test the second channel for data communication; and sending a data stream to the second-end apparatus through the first channel and the second channel.

Abstract: A fast equalization method is provided, which includes: storing a receive parameter and a transmit parameter, of each of a primary chip and a secondary chip, that meet a link stability requirement and that are obtained when link equalization is previously performed; and when determining that link equalization needs to be performed, configuring, as first fast equalization timeout duration, a larger value in initial fast equalization timeout duration of the primary chip and initial fast equalization timeout duration of the secondary chip, and invoking the foregoing receive and transmit parameters, so that the primary chip and the secondary chip perform a current time of link equalization based on the first fast equalization timeout duration and the foregoing transmit and receive parameters.

Abstract: A fast equalization method is provided, which includes: storing a receive parameter and a transmit parameter, of each of a primary chip and a secondary chip, that meet a link stability requirement and that are obtained when link equalization is previously performed; and when determining that link equalization needs to be performed, configuring, as first fast equalization timeout duration, a larger value in initial fast equalization timeout duration of the primary chip and initial fast equalization timeout duration of the secondary chip, and invoking the foregoing receive and transmit parameters, so that the primary chip and the secondary chip perform a current time of link equalization based on the first fast equalization timeout duration and the foregoing transmit and receive parameters.

Abstract: A fast equalization method is provided, which includes: storing a receive parameter and a transmit parameter, of each of a primary chip and a secondary chip, that meet a link stability requirement and that are obtained when link equalization is previously performed; and when determining that link equalization needs to be performed, configuring, as first fast equalization timeout duration, a larger value in initial fast equalization timeout duration of the primary chip and initial fast equalization timeout duration of the secondary chip, and invoking the foregoing receive and transmit parameters, so that the primary chip and the secondary chip perform a current time of link equalization based on the first fast equalization timeout duration and the foregoing transmit and receive parameters.

Abstract: A fast equalization method is provided, which includes: storing a receive parameter and a transmit parameter, of each of a primary chip and a secondary chip, that meet a link stability requirement and that are obtained when link equalization is previously performed; and when determining that link equalization needs to be performed, configuring, as first fast equalization timeout duration, a larger value in initial fast equalization timeout duration of the primary chip and initial fast equalization timeout duration of the secondary chip, and invoking the foregoing receive and transmit parameters, so that the primary chip and the secondary chip perform a current time of link equalization based on the first fast equalization timeout duration and the foregoing transmit and receive parameters.