Abstract: A manufacturing method of a memory includes: providing a substrate and a bit line contact layer; forming a dummy bit line structure on top of the bit line contact layer; forming a spacer layer on the sidewall of both the dummy bit line structure and the bit line contact layer; forming a dielectric layer on the sidewall of the spacer layer; forming a sacrificial layer filling the area between adjacent dummy bit line structures, wherein the sacrificial layer covers the sidewall of the dielectric layer; after the sacrificial layer is formed, removing the dummy bit line structure; forming a bit line conductive portion which fills the hole and covers the bit line contact layer; and, after the bit line conductive portion is formed, removing the spacer layer.

Abstract: The present disclosure provides a semiconductor structure and a storage circuit that implements the storage structure of a magnetoresistive random access memory (MRAM) based on a dynamic random access memory (DRAM) fabrication platform.

Abstract: Embodiment relates to the field of semiconductor technologies, and proposes a semiconductor device and a fabrication method thereof. The semiconductor device includes: a substrate, a semiconductor structure, an insulating layer, and a conductive layer. The semiconductor structure is positioned on a side of the substrate and includes a first semiconductor structure and a second semiconductor structure, wherein the first semiconductor structure and the second semiconductor structure form a PN junction. The insulating layer is positioned on a side of the semiconductor structure facing away from the substrate. The conductive layer is positioned on a side of the insulating layer facing away from the substrate, and an orthographic projection of the conductive layer on the substrate at least partially overlaps an orthographic projection of the PN junction on the substrate.

Abstract: A method for manufacturing a buried gate and a method for manufacturing a semiconductor device are disclosed. The method for manufacturing the buried gate includes that: a trench is provided on an active region of a substrate; a gate structure is filled in a bottom of the trench, and a trench sidewall above the gate structure is exposed; an epitaxial layer is grown on the exposed trench sidewall with an epitaxial growth process, in which the epitaxial layer does not close the trench; and an isolation layer is filled in the trench.

Abstract: A method for manufacturing a memory includes: providing a substrate and multiple discrete pseudo bit line contact layers, a plurality of active areas being provided in the substrate, and each bit line contact layer being electrically connected to the active areas; forming pseudo bit line structures at tops of the pseudo bit line contact layers; forming sacrificial layers that fill regions between the adjacent pseudo bit line structures and are located on side walls of the pseudo bit line structures and the pseudo bit line contact layers; after forming the sacrificial layers, removing the pseudo bit line structures to form through holes exposing the pseudo bit line contact layers; removing the pseudo bit line contact layers to form through holes in the substrate; and forming bit line contact layers that fill the through holes in the substrate and are electrically connected to the active areas.

Abstract: A method for manufacturing a semiconductor structure includes: providing a substrate; forming a first shielding layer on the substrate; forming a first electrode penetrating the first shielding layer; forming a storage structure on the first electrode; forming a second shielding layer on the top surface and sidewalls of the storage structure, wherein the first shielding layer and the second shielding layer combine into one integrated shielding layer; and forming a second electrode which penetrates the shielding layer and electrically connects to the storage structure.

Abstract: A method of forming a gate structure on a substrate with increased charge mobility. In some embodiments, the method may include depositing an amorphous carbon layer on a silicon carbide layer on the substrate to form a capping layer on the silicon carbide layer, annealing the silicon carbide layer at a temperature of greater than approximately 1800° C., forming a hard mask on the silicon carbide layer by patterning the amorphous carbon layer, etching a trench structure of the gate structure into the silicon carbide layer using the hard mask, removing the hard mask to expose the silicon carbide layer, depositing a silicon dioxide layer on the silicon carbide layer using an ALD process, performing at least one interface treatment on the silicon dioxide layer, depositing a gate oxide layer of the gate structure on the silicon dioxide layer, and depositing a gate material on the gate oxide layer.

Abstract: Embodiments of the present disclosure provide a method of manufacturing a semiconductor structure. The semiconductor structure includes a peripheral area and an array area, and the method of manufacturing a semiconductor structure includes: providing a substrate; where the substrate in the peripheral area includes an active layer; a first isolation layer is further provided on the active layer; forming a buried word line in the substrate in the array area; where a second isolation layer is further provided on the buried word line; the buried word line includes a first conductive layer and a second conductive layer; patterning the first isolation layer and the second isolation layer by dry etching to form first through holes and a second through hole; where the first through holes expose a top surface of the active layer, and the second through hole exposes the second conductive layer.

Abstract: Embodiments described herein relate to methods and materials for fabricating semiconductor devices, such as memory devices and the like. In one embodiment, a memory layer stack includes materials having differing etch rates in which one material is selectively removed to form an airgap in the device structure. In another embodiment, silicon containing materials of a memory layer stack are doped or fabricated as a silicide material. In another embodiment, a silicon nitride material is utilized as an interfacial layer between oxide containing and silicon containing layers of a memory layer stack.

Abstract: The present invention relates to the field of semiconductor manufacturing technologies, in particular to a semiconductor device and a method of forming the same. The method of forming the semiconductor device includes the following steps: forming a substrate with a trench, a gate dielectric layer covering an inner wall of the trench, a barrier layer covering a portion of a surface of the gate dielectric layer, and a first gate layer filled on an surface of the barrier layer being disposed in the trench; removing a portion of the barrier layer to form an groove located between the first gate layer and the gate dielectric layer; forming a channel dielectric layer at least covering an inner wall of the groove and a top surface of the first gate layer; and forming a second gate layer at least partially filling an interior of the groove.

Abstract: A method for manufacturing a semiconductor structure and a semiconductor structure can improve performance of the semiconductor structure. The method for manufacturing the semiconductor structure includes: forming bit line structures on a substrate, each of the bit line structures including a conductive layer, a transition layer and a covering layer stacked sequentially, and a width of the transition layer being smaller than a width of the conductive layer; and forming air gaps on a top surface of the conductive layer and side surfaces of the transition layer. The air gaps not only can reduce influence of the covering layer on the conductive layer to prevent the resistance of the conductive layer from increasing, but also can reduce the parasitic capacitance between the bit line structures and the surrounding structures thereof, thereby improving the performance of the semiconductor structure.

Abstract: A semiconductor structure and a forming method thereof are disclosed in the embodiments of the present disclosure. The semiconductor structure includes: a base, wherein a gate dielectric layer defining a groove is provided in the base, a source region and a drain region are located on two opposite sides at a top of the groove, and the groove has an extension direction parallel to a surface of the base; a first gate, including a first work function layer and a first conductive layer, wherein the first work function layer covers a bottom surface and partial sidewall of the groove, and the first conductive layer covers a surface of the first work function layer; and a second gate, including a second work function layer and a second conductive layer, wherein the second gate is laminated on the first gate and has a top surface lower than the surface of the base.

Abstract: Provided are a manufacturing method of a semiconductor structure, and a semiconductor structure. The manufacturing method includes: providing a substrate; forming a plurality of bit line structures distributed at intervals on the substrate, each of the bit line structures including a conductive structure, a conductive barrier block and an insulative structure which are stacked sequentially, and the width of the conductive barrier block being less than the width of the conductive structure; and forming an air gap in contact with a side wall of each of the bit line structures.

Abstract: A method for forming a semiconductor structure can include the following steps. A substrate and an insulating layer that are stacked are provided, the substrate having a plurality of storage node contact structures spaced apart from each other. A grid-like upper electrode layer is formed on a surface of the insulating layer, where the upper electrode layer has a plurality of meshes penetrating the upper electrode layer, and an orthographic projection of each of the meshes on the insulating layer and an orthographic projection of a storage node contact structure on the insulating layer have an overlapping area. A dielectric layer is formed on a side wall of each mesh. The insulating layer exposed from the mesh is removed to expose the storage node contact structure. A lower electrode layer is formed inside each mesh.

Abstract: A method of manufacturing a semiconductor structure and a semiconductor structure are disclosed in embodiments of the present disclosure. The method of manufacturing a semiconductor includes: providing a base; and forming an electrical contact layer, a bottom barrier layer, and a conductive layer that are sequentially stacked on the base, where a material of the conductive layer includes molybdenum.

Abstract: The present disclosure provides a semiconductor structure and a storage circuit that implements the storage structure of a magnetoresistive random access memory (MRAM) based on a dynamic random access memory (DRAM) fabrication platform.

Abstract: A method for manufacturing a memory includes: providing a substrate and multiple discrete pseudo bit line contact layers, a plurality of active areas being provided in the substrate, and each bit line contact layer being electrically connected to the active areas; forming pseudo bit line structures at tops of the pseudo bit line contact layers; forming sacrificial layers that fill regions between the adjacent pseudo bit line structures and are located on side walls of the pseudo bit line structures and the pseudo bit line contact layers; after forming the sacrificial layers, removing the pseudo bit line structures to form through holes exposing the pseudo bit line contact layers; removing the pseudo bit line contact layers to form through holes in the substrate; and forming bit line contact layers that fill the through holes in the substrate and are electrically connected to the active areas.

Abstract: A method for manufacturing a memory includes the following operations. A substrate and a plurality of separate initial bit line contact structures are provided, in which a plurality of active regions are formed in the substrate, and each of the initial bit line contact structures is electrically connected with the active regions, and each of the initial bit line contact structures is partially located in the substrate. Pseudo-bit line structures on the tops of the initial bit line contact structures are formed. The initial bit line contact structures are etched to form bit line contact layers and gaps between the substrate and the side walls of the bit line contact layers. First dielectric layers are formed on the side walls of the pseudo-bit line structures, in which the first dielectric layers are also located right above the gaps.

Abstract: A manufacturing method of a memory includes: providing a substrate and a bit line contact layer; forming a dummy bit line structure on top of the bit line contact layer; forming a spacer layer on the sidewall of both the dummy bit line structure and the bit line contact layer; forming a dielectric layer on the sidewall of the spacer layer; forming a sacrificial layer filling the area between adjacent dummy bit line structures, wherein the sacrificial layer covers the sidewall of the dielectric layer; after the sacrificial layer is formed, removing the dummy bit line structure; forming a bit line conductive portion which fills the hole and covers the bit line contact layer; and, after the bit line conductive portion is formed, removing the spacer layer.

Abstract: Embodiment relates to the field of semiconductor technologies, and proposes a semiconductor device and a fabrication method thereof. The semiconductor device includes: a substrate, a semiconductor structure, an insulating layer, and a conductive layer. The semiconductor structure is positioned on a side of the substrate and includes a first semiconductor structure and a second semiconductor structure, wherein the first semiconductor structure and the second semiconductor structure form a PN junction. The insulating layer is positioned on a side of the semiconductor structure facing away from the substrate. The conductive layer is positioned on a side of the insulating layer facing away from the substrate, and an orthographic projection of the conductive layer on the substrate at least partially overlaps an orthographic projection of the PN junction on the substrate.