Abstract: An apparatus is provided, comprising: a first circuitry configured to generate a signal at a voltage level for one or more components; a second circuitry configured to generate a clock at a frequency level for the one or more components; a third circuitry configured to intermittently measure a current level of the signal; a fourth circuitry configured to estimate a first average of the current level of the signal over a first time-window; and a fifth circuitry configured to, in response to the first average being higher than a threshold average current, facilitate regulating one or both the voltage level of the signal or the frequency level of the clock.

Abstract: A system, method and device for storing branch predictions in a queue that may be connected to a branch prediction unit, and for delivering the stored predictions to an instruction fetch unit. A look up may be made of for example two sequential lines, and for example a segmented cache of a branch prediction unit may generate predictions of an address having an even numbered index by referring to for example a first side of the cache, and an address with an odd numbered index by referring to for example a second side of the cache. Branch predictions for two sequential lines may be generated during for example a prediction period such as two clock cycles. In some embodiments, a next instruction pointer of a branch prediction unit may be independent or decoupled from of a next instruction pointer of an instruction fetch unit.

Abstract: A system and method of early branch prediction in a processor to evaluate, typically before a full branch prediction is made, ways in a branch target buffer to determine if any of said ways corresponds to a valid unconditional branch, and upon such determination, to generate a signal to prevent a read of a next sequential chunk.

Abstract: Briefly, a method and apparatus of branch prediction is provided. The branch prediction may be done by performing a XOR operation between MSB of set bits of a path register with LSB of set bits of an instruction pointer address register to provide a global index, and by performing a XOR operation of LSB tag bits of the path register with MSB tag bits of the instruction pointer address register and providing a tag index. There may be multiplexing between a global prediction to a local prediction.

Abstract: A trace management architecture to enable the reuse of uops within one or more repeated traces. More particularly, embodiments of the invention relate to a technique to prevent multiple accesses to various functional units within a trace management architecture by reusing traces or sequences of traces that are repeated during a period of operation of the microprocessor, avoiding performance gaps due to multiple trace cache accesses and increasing the rate at which uops can be executed within a processor.

Abstract: A system, method and device for storing branch predictions in a queue that may be connected to a branch prediction unit, and for delivering the stored predictions to an instruction fetch unit. A look up may be made of for example two sequential lines, and for example a segmented cache of a branch prediction unit may generate predictions of an address having an even numbered index by referring to for example a first side of the cache, and an address with an odd numbered index by referring to for example a second side of the cache. Branch predictions for two sequential lines may be generated during for example a prediction period such as two clock cycles. In some embodiments, a next instruction pointer of a branch prediction unit may be independent or decoupled from of a next instruction pointer of an instruction fetch unit.

Abstract: A system and method of early branch prediction in a processor to evaluate, typically before a full branch prediction is made, ways in a branch target buffer to determine if any of said ways corresponds to a valid unconditional branch, and upon such determination, to generate a signal to prevent a read of a next sequential chunk.

Abstract: A processor including a branch prediction unit, wherein various techniques can be used to decrease branch prediction unit access, possibly saving power. Whether or not a branch prediction target needs updating may be stored, and thus it may be known whether or not the branch prediction unit needs to be accessed after the initial access. Which way corresponds to the prediction may be stored, decreasing the amount of subsequent accesses. Use information (e.g., least recently used information) may be updated at the time of the first access of the branch prediction unit, possibly eliminating the need for a later use information update. A branch prediction unit update or allocate, or update or allocate attempt, may be performed prior to the execute stage.

Abstract: Briefly, a method and apparatus of branch prediction is provided. The branch prediction may be done by performing a XOR operation between MSB of set bits of a path register with LSB of set bits of an instruction pointer address register to provide a global index, and by performing a XOR operation of LSB tag bits of the path register with MSB tag bits of the instruction pointer address register and providing a tag index. There may be multiplexing between a global prediction to a local prediction.