Abstract: The disclosure discloses various systems, apparatuses, devices, and methods for verification and testing of hardware description language (HDL) and field-programmable gate array (FPGA) designs. A waveform dump generated in a verification environment or in-FPGA environment can be used to prepare a stimulus file that is configured to reduce the time needed to fix an error/issue found in an HDL/FPGA design. In the verification environment, the stimulus file can reduce the simulation time of an HDL design needed to reproduce the error/issue encountered in a full cycle simulation. Similarly, in the in-FPGA environment, the stimulus file can reduce the simulation time needed to reproduce the error/issue encountered in the FPGA hardware test. In both cases, the techniques for configuring stimulus file can accelerate the process of debugging, testing, and verifying a design using simulation.

Abstract: A plurality of commands is received from at least one application. A command of the plurality of commands is to be performed by a Data Storage Device (DSD) after one or more conditions have been satisfied by the DSD. The plurality of commands is enqueued and the command is enqueued with the one or more conditions for performing the command. It is determined whether the one or more conditions have been satisfied by the DSD, and in response to determining that the one or more conditions have been satisfied by the DSD, the command is sent to the DSD for performance of the command.

Abstract: A storage device includes a non-volatile memory (NVM) and a storage device controller. The storage device controller includes a NVM interface coupled to the NVM and one or more task queues. The storage device controller is operable to pick a task from one or more queues of the storage device. The task is parsed based upon presence of an extra header segment with an execution condition. The task without the extra header segment is sent to execution. Whether the execution condition of the extra header segment of the task is met is determined. The task with the execution condition met is sent to execution. The task with the execution condition unmet is postponed.

Abstract: A plurality of commands is received from at least one application. A command of the plurality of commands is to be performed by a Data Storage Device (DSD) after one or more conditions have been satisfied by the DSD. The plurality of commands is enqueued and the command is enqueued with the one or more conditions for performing the command. It is determined whether the one or more conditions have been satisfied by the DSD, and in response to determining that the one or more conditions have been satisfied by the DSD, the command is sent to the DSD for performance of the command.

Abstract: A storage device includes a non-volatile memory (NVM) and a storage device controller. The storage device controller includes a NVM interface coupled to the NVM and one or more task queues. The storage device controller is operable to pick a task from one or more queues of the storage device. The task is parsed based upon presence of an extra header segment with an execution condition. The task without the extra header segment is sent to execution. Whether the execution condition of the extra header segment of the task is met is determined. The task with the execution condition met is sent to execution. The task with the execution condition unmet is postponed.

Abstract: A storage device includes a non-volatile memory (NVM) and a storage device controller. The storage device controller includes a NVM interface coupled to the NVM and one or more task queues. The storage device controller is operable to pick a task from one or more queues of the storage device. The task is parsed based upon presence of an extra header segment with an execution condition. The task without the extra header segment is sent to execution. Whether the execution condition of the extra header segment of the task is met is determined. The task with the execution condition met is sent to execution. The task with the execution condition unmet is postponed.

Abstract: A method of searching a database that includes executing a trie search algorithm on a first portion of data in the database, returning a tag narrowing a location of the first portion of data to optimize the database, and performing a directed search of the optimized database by executing the trie search algorithm again on the optimized database, where the trie search algorithm is an information retrieval data structure using a M-ary tree where each node consists of a M-positional vector of pointers.

Abstract: A method of searching a database that includes executing a trie search algorithm on a first portion of data in the database, returning a tag narrowing a location of the first portion of data to optimize the database, and performing a directed search of the optimized database by executing the trie search algorithm again on the optimized database, where the trie search algorithm is an information retrieval data structure using a M-ary tree where each node consists of a M-positional vector of pointers.

Abstract: A data storage device includes a non-volatile memory and host interface circuitry. The host interface circuitry is configured, in response to receiving a first command from a host device, to access a table to determine whether to reject the first command based on an operating state of the data storage device. The data storage device also includes a processor coupled to the non-volatile memory and to the host interface circuitry. The processor is configured to program the table.

Abstract: A data storage device includes a non-volatile memory and host interface circuitry. The host interface circuitry is configured, in response to receiving a first command from a host device, to access a table to determine whether to reject the first command based on an operating state of the data storage device. The data storage device also includes a processor coupled to the non-volatile memory and to the host interface circuitry. The processor is configured to program the table.

Abstract: An LDPC decoder, applicable to LDPC codes including codes where check nodes within the same group are connected to a common bit node, successively processes groups of check nodes in a particular iteration, including updating bit nodes in that same iteration responsive to messages generated in response to processing a group of check nodes. Within an iteration, the LDPC decoder may also track the number of unresolved parity check equations, and cease iterating or output to an outer block decoder if that number reaches a local minima or standard minimum, falls below a predetermined threshold, or its rate of change falls below a predetermined threshold, indicating a lack of convergence or false convergence condition. The LDPC decoder may also provide a feedback assist to a demodulator. Also, a novel memory configuration may store messages generated by the decoder in the course of check node processing.

Abstract: A multi-channel decoder system has a decoder core at least a portion of which is configurable as a LDPC decoder that, during decoding processing, divides check nodes of a node representation of a LDPC code into a plurality of groups, and, during an iteration, sequentially processes the groups while processing in parallel the check nodes within each group, thus improving decoding throughput.

Abstract: An LDPC decoder, applicable to LDPC codes including codes where check nodes within the same group are connected to a common bit node, successively processes groups of check nodes in a particular iteration, including updating bit nodes in that same iteration responsive to messages generated in response to processing a group of check nodes. Within an iteration, the LDPC decoder may also track the number of unresolved parity check equations, and cease iterating or output to an outer block decoder if that number reaches a local minima or standard minimum, falls below a predetermined threshold, or its rate of change falls below a predetermined threshold, indicating a lack of convergence or false convergence condition. The LDPC decoder may also provide a feedback assist to a demodulator. Also, a novel memory configuration may store messages generated by the decoder in the course of check node processing.

Abstract: A multi-channel decoder system has a decoder core, at least a portion of which comprises or is configurable as a LDPC decoder, a plurality of channels to and from the decoder core, and control logic for controlling application of the decoder core to data carried by one or more of the channels.

Abstract: Systems and related methods are described for (1) determining one or more state probabilities for one or more states in a trellis representation; (2) determining an estimate of or extrinsic output for a bit using a trellis representation; (3) performing a MAX* 2?>1 operation; and (4) computing forward state probabilities in a forward mode of operation and computing backward state probabilities in a backward mode of operation. Combinations of the foregoing are also described.

Abstract: Systems and related methods are described for (1) determining one or more state probabilities for one or more states in a trellis representation; (2) determining an estimate of or extrinsic output for one or more bits using a trellis representation; (3) determining a branch metric for a branch in a trellis representation; (4) performing a MAX*2->1 operation; (5) performing a MAX*2p->1 operation, where p is an integer of two or more, through a hierarchical arrangement of MAX*2->1 operations; and (6) computing forward state probabilities in a forward mode of operation and computing backward state probabilities in a backward mode of operation. Combinations of the foregoing are also described.

Abstract: Systems and related methods are described for (1) determining one or more state probabilities for one or more states in a trellis representation; (2) determining an estimate of or extrinsic output for one or more bits using a trellis representation; (3) determining a branch metric for a branch in a trellis representation; (4) performing a MAX*2->1 operation; (5) performing a MAX*2p->1 operation, where p is an integer of two or more, through a hierarchical arrangement of MAX*2->1 operations; and (6) computing forward state probabilities in a forward mode of operation and computing backward state probabilities in a backward mode of operation. Combinations of the foregoing are also described.