Abstract: A computer-based system and method for providing a distributed write buffer in a storage system, including: obtaining a write request at a primary storage server to store data associated with the write request in a non-volatile storage of the primary storage server; and storing the data associated with the write request in a persistent memory of the primary storage server or in a persistent memory of an auxiliary storage server based on presence of persistent memory space in the primary storage server. The write request may be acknowledged by the primary storage server after storing the data associated with the write request in the persistent memory of the primary storage server or in the persistent memory of the auxiliary storage server.

Abstract: Systems and methods of managing data storage, on non-volatile memory (NVM) media, by at least one processor may include: receiving a first storage request, to store a first data block on the NVM media; storing content of the first data block on a cache memory module; scheduling a future movement action of the content of the first data block from the cache memory module to the NVM media; and moving, transmitting or copying the content of the first data block from the cache memory module to at least one NVM device of the NVM media, according to the scheduled movement action.

Abstract: computer-based system and method for selecting a write unit size for a block storage device, includes performing a plurality of sequences of I/O operations to the block storage device, each sequence having a write unit size from a plurality of write unit sizes; collecting performance metrics of the sequences of I/O operations; and selecting the write unit size for the block storage device from the plurality of write unit sizes based on the performance metrics. In some cases, preconditioning is performed prior to performing the plurality of sequences of I/O operations by emptying the block storage device; and writing data to the block storage device to fill the block storage device above a predetermined level.

Abstract: A field programmable gate array (FPGA), that includes a trusted FPGA logic, an untrusted FPGA logic and a monitor; wherein the monitor is configured to monitor the untrusted FPGA logic and prevent the untrusted FPGA logic from violating predefined constrains imposed on an operation of the untrusted FPGA logic; wherein the predefined constraints are stored in a memory region of the FPGA that is not accessible to the untrusted FPGA logic.

Abstract: A system and a method of managing storage of cached data objects on a non-volatile memory (NVM) computer storage media including at least one NVM storage device, by at least one processor, may include: receiving one or more data objects having respective Time to Live (TTL) values; storing the one or more data objects and respective TTL values at one or more physical block addresses (PBAs) of the storage media; and performing a garbage collection (GC) process on one or more PBAs of the storage media based on at least one TTL value stored at a PBA of the storage media.

Abstract: A method for accessing a storage system, the method may include receiving a block call, from a processor that executes an application and by a storage engine of a computer that is coupled to a storage system; generating, by the storage engine and based on the block call, a key value call; and sending the key value call to a key value frontend of the storage system.

Abstract: A storage system that includes an in-line hardware accelerator, a solid-state drive (SSD) unit, a central processing unit (CPU), a volatile memory module, and an accelerator memory module that is coupled to the in-line hardware accelerator or belongs to the in-line hardware accelerator; wherein the in-line hardware accelerator is directly coupled to the SSD unit, the volatile memory and the non-volatile memory; wherein the CPU is directly coupled to the volatile memory and to the non-volatile memory; wherein the in-line hardware accelerator is configured to manage access to the SSD unit; wherein the in-line accelerator is configured to retrieve data stored in the volatile memory module and the non-volatile memory module without involving the CPU.

Abstract: A method and a system for accelerating computer data garbage collection (GC) on a non-volatile memory (NVM) computer storage device may include: monitoring, by a processor, a data validity parameter of at least one physical write unit (PWU), where the PWU may include a plurality of physical data pages of the NVM device; sending at least one GC command from the processor to an accelerator associated with the NVM device, based on the monitored data validity parameter; copying, by the accelerator, a plurality of data-objects stored on at least one first PWU, to a read address space comprised within the accelerator; copying valid data-objects from the read address space to a write address space comprised within the accelerator until the amount of data in the write address space exceeds a predefined threshold; and storing, by the accelerator, the data content in at least one second PWU in the NVM media.

Abstract: A system and method of managing non-volatile computer storage media may include: receiving at least one value of at least one parameter, including for example: a size of data objects, a frequency of data write requests, a size of write units (WUs) and a required write amplification value; setting a cyclic write pointer to point to a WU having a logical address space; setting a cyclic garbage collection (GC) pointer to point to a WU having a logical address space, located ahead of the WU pointed by the write pointer; performing GC on the WU pointed by the GC pointer; and incrementing the cyclic GC pointer to point to a next WU according to the value of the cyclic write pointer and according to the at least one received parameter value.

Abstract: A nonvolatile memory system, a nonvolatile memory controller and a method for reducing latency of a memory controller are disclosed. The nonvolatile memory system includes a read circuit that performs background reads of an indicator page of each block to identify outlier blocks. A background reference positioning circuit performs background reads of representative pages of the outlier block at threshold voltage offsets to identify sets of updated threshold voltage offset values. Upon endurance events, retention timer events and read disturb events at a closed block background reads are performed of representative pages of the closed block at threshold voltage offsets to identify sets of updated threshold voltage offset values.

Abstract: A nonvolatile memory system, a nonvolatile memory controller and a method for reducing latency of a memory controller are disclosed. The nonvolatile memory system includes a read circuit that performs background reads of an indicator page of each block to identify outlier blocks. A background reference positioning circuit performs background reads of representative pages of the outlier block at threshold voltage offsets to identify sets of updated threshold voltage offset values. Upon endurance events, retention timer events and read disturb events at a closed block background reads are performed of representative pages of the closed block at threshold voltage offsets to identify sets of updated threshold voltage offset values.

Abstract: A method for determining at least one parameter for a particular AAL2 channel identifier (AAL2-CID), according to which the behavior of the transmission of the user information stream is determined per application. Preferably, the present invention enables the QOS (quality of service) for the user application to be determined by setting a plurality of such parameters for a specific AAL2 CID. The present invention preferably encompasses the ability to determine any parameter that is usually set for the ATM channel to instead be set for the CID separately. These parameters may be dynamically adjusted according to the real-time state of the system, channel and the specific CID. Additionally the selection and usage of said parameters may also be influenced by the real time state of the system, channel and the specific CID. Examples of such parameters include, but are not limited to, traffic type, priority, any type of QOS parameter, timing parameters, and so forth.

Abstract: In some embodiments of the present invention, applications presenting user information streams at a service access point (SAP) to AAL-2 above the Common Part Sublayer (CPS) may provide values for predefined parameters that may determine how frames of information in the user information streams are segmented in run-time into CPS packets and packed into CPS protocol data units (CPS-PDU), each of which forms the payload of an ATM cell. These parameter values may be defined per channel identifier (CID) or for a group of CIDs.

Abstract: A method for determining at least one parameter for a particular AAL2 channel identifier (AAL2-CID), according to which the behavior of the transmission of the user information stream is determined per application. Preferably, the present invention enables the QOS (quality of service) for the user application to be determined by setting a plurality of such parameters for a specific AAL2 CID. The present invention preferably encompasses the ability to determine any parameter that is usually set for the ATM channel to instead be set for the CID separately. These parameters may be dynamically adjusted according to the real-time state of the system, channel and the specific CID. Additionally the selection and usage of said parameters may also be influenced by the real time state of the system, channel and the specific CID. Examples of such parameters include, but are not limited to, traffic type, priority, any type of QOS parameter, timing parameters, and so forth.

Abstract: In some embodiments of the present invention, applications presenting user information streams at a service access point (SAP) to AAL-2 above the Common Part Sublayer (CPS) may provide values for predefined parameters that may determine how frames of information in the user information streams are segmented in run-time into CPS packets and packed into CPS protocol data units (CPS-PDU), each of which forms the payload of an ATM cell. These parameter values may be defined per channel identifier (CID) or for a group of CIDs.

Abstract: A reassembly unit comprising of a reassembly buffer and a control unit and a detector. The reassembly unit monitors an amount of data AMD stored in the reassembly register and compares AMD to four thresholds, TS1, TS2, TS3 and TS4. TS1 and TS4 define the size of the reassembly buffer. TS2 defines the delay of reassembly unit 40. A difference between TS1 and TS2 defines an underflow recovery period in which data is not read out of the buffer. A difference between TS4 and TS3 define an overflow recovery period in which data is not written in the buffer. The four thresholds can be changed during an operation of the reassembly unit, allowing a user to adjust the thresholds according to the state of the reassembly unit.

Abstract: A system and a method of the present invention for implementing a combined use Timer_CU within an ATM transmitter. The ATM transmitter being able to handle a plurality of ATM channels, at least one of the channel being an ATM AAL2 channel. The ATM channels can provide ATM-cells at different traffic parameters, such as, for example, different cell or bit rate, priorities, and bursts. The system schedules channels in a first table by channel identifiers. Cyclical pointers to this first table advance (i) at every time slot, (ii) within a time slot, whereas (iii) CPS-Packets with one or more octets already packed wait at most the duration of a Timer_CU before being scheduled to be sent by CPS transmitter to ATM transmitter. Conveniently, the schedule scheme is based upon a scheduling table comprising of a plurality of time slots.