Patents by Inventor Eran Lipp

Eran Lipp has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11963309
    Abstract: Processes for laminating a conductive-lubricant coated Printed Circuit Board (PCB) are disclosed. An example laminated PCB may include a lamination stack that may further include a core, an adhesive layer, and at least one graphene-metal structure or at least one hexagonal Boron Nitride metal (h-BN-metal) structure. The materials of the PCB may change in accordance with the invention described herein, including the materials of the core, the materials of the conductive-lubricant coatings, or the metal layers of the conductive-lubricant-metal structures. Doping processes for each change in materials used are also described herein. The conductive-lubricant of the conductive-lubricant-metal structure will promote high frequency performance and heat management within the PCB. Furthermore, a removal process of those materials post-lamination is described herein to promote protection of materials and subsequent removal of protective layers without breakage or tearing.
    Type: Grant
    Filed: July 1, 2021
    Date of Patent: April 16, 2024
    Assignees: MELLANOX TECHNOLOGIES, LTD., BAR-ILAN UNIVERSITY, PCB TECHNOLOGIES LTD.
    Inventors: Boaz Atias, Elad Mentovich, Yaniv Rotem, Doron Naveh, Adi Levi, Yosi Ben-Naim, Yaad Eliya, Shlomo Danino, Eran Lipp, Alon Rubinstein, Ran Hasson Ruso
  • Publication number: 20230007788
    Abstract: Processes for laminating a conductive-lubricant coated Printed Circuit Board (PCB) are disclosed. An example laminated PCB may include a lamination stack that may further include a core, an adhesive layer, and at least one graphene-metal structure or at least one hexagonal Boron Nitride metal (h-BN-metal) structure. The materials of the PCB may change in accordance with the invention described herein, including the materials of the core, the materials of the conductive-lubricant coatings, or the metal layers of the conductive-lubricant-metal structures. Doping processes for each change in materials used are also described herein. The conductive-lubricant of the conductive-lubricant-metal structure will promote high frequency performance and heat management within the PCB. Furthermore, a removal process of those materials post-lamination is described herein to promote protection of materials and subsequent removal of protective layers without breakage or tearing.
    Type: Application
    Filed: July 1, 2021
    Publication date: January 5, 2023
    Inventors: Boaz ATIAS, Elad Mentovich, Yaniv Rotem, Doron Naveh, Adi Levi, Yosi Ben-Naim, Yaad Eliya, Shlomo Danino, Eran Lipp, Alon Rubinsten
  • Publication number: 20220377912
    Abstract: Processes for laminating a graphene-coated printed circuit board (PCB) are disclosed. An example laminated PCB may include a lamination stack that may include an inner core, an adhesive layer, and at least one graphene-metal structure. Pressure and heat—which may be applied under vacuum or controlled gas atmosphere—may be applied to the lamination stack, after all materials have been placed. The graphene of the graphene-metal structure is designed to promote high frequency performance and heat management within the PCB.
    Type: Application
    Filed: July 1, 2021
    Publication date: November 24, 2022
    Inventors: Boaz ATIAS, Elad MENTOVICH, Yaniv ROTEM, Doron NAVEH, Adi LEVI, Yosi BEN-NAIM, Yaad ELIYA, Shlomo DANINO, Eran LIPP
  • Patent number: 10522388
    Abstract: An SOI IC includes a polysilicon/silicon plug extending through the buried insulation layer between a P-type handle layer and a P-type device layer. An N-type well region is formed in the device layer over the polysilicon/silicon plug, and then a high-voltage (HV) device is formed in the well region such that part of its drift region is located over the polysilicon/silicon plug. Doping of the well region, the polysilicon/silicon plug and the handle layer is coordinated to form a P-N junction diode that couples the HV device, by way of the polysilicon/silicon plug, to a ground potential applied to the handle layer, thereby increasing the HV device's breakdown voltage by expanding its depletion region to include the handle layer. The polysilicon/silicon plug grows in holes formed through the insulation layer during the epitaxial silicon growth process used to form the device layer.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: December 31, 2019
    Assignee: Tower Semiconductor Ltd.
    Inventors: Einat Ophir Arad, Sharon Levin, Allon Parag, Eran Lipp, Yosef Avrahamov