Abstract: A data processing system comprises a task scheduling device arranged to schedule a plurality of tasks; and a plurality of processing units, at least some of which being adapted to execute one or more assigned tasks of the plurality of tasks and, for each assigned task, to provide to the task scheduling device at least a task status event which indicates when an execution of the assigned task is finished; wherein the task scheduling device comprises a task scheduler controller unit arranged to assign one or more of the plurality of tasks, each to a corresponding one of the processing units being adapted to execute the assigned task, in response to receiving one or more of the task status events associated with one or more previously assigned tasks.

Abstract: A processor for performing a block floating point Fast Fourier Transform having improved signal to quantization noise ratio performance. In the radix-2 Decimation In Time algorithm, overflow between stages is prevented by a scale down by two invoked by comparison with a fixed comparison constant. Unfortunately, the fixed comparison constant is not always optimum for maximizing the signal to quantization noise ratio, which is degraded by excessive scale down. Moreover, current mechanisms are limited to the radix-2 block floating point FFT. The processor of the present invention provides the programmer with a FFT compare register which is loadable under program control, thus allowing the programmer to adjust the threshold at which scale down of the stage output is activated for better control over the signal to quantization noise ratio. In addition, the present invention supports other FFT structures besides the radix-2 block floating point FFT.