Patents by Inventor Eran Weis

Eran Weis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7921391
    Abstract: Apparatus, methods, and computer readable code for computing parameters related to layout schemes of integrated circuits are disclosed herein. In some embodiments, an actual layout scheme is computed, for example, for a netlist. In some embodiments, one o or more layout schemes are scored based on, for example, susceptibility to failure and/or yield in manufacturing.
    Type: Grant
    Filed: June 4, 2006
    Date of Patent: April 5, 2011
    Assignee: Daro Semiconductors Ltd.
    Inventor: Eran Weis
  • Publication number: 20100131907
    Abstract: Apparatus, methods, and computer readable code for computing parameters related to layout schemes of integrated circuits are disclosed herein. In some embodiments, an actual layout scheme is computed, for example, for a netlist. In some embodiments, one o or more layout schemes are scored based on, for example, susceptibility to failure and/or yield in manufacturing.
    Type: Application
    Filed: June 4, 2006
    Publication date: May 27, 2010
    Inventor: Eran Weis
  • Patent number: 6694494
    Abstract: A method of designing a single-chip circuit system that includes several dissimilar (digital, analog, memory, power, RF, electro-optical) modules, and the system so designed. A prior art method is used for an initial design of the system, including signal and power conductors connecting the modules. Signal conductors are initially designed for current densities in a first range. Power conductors are initially designed for current densities in a second range. For each signal conductor, an initial value of a design parameter is changed to increase the current density into a higher third range, the resistance of the conductor is reduced, and the parameter value is restored to its initial value. For each power conductor, an initial value of a design parameter is changed to decrease the current density into a lower fourth range, the resistance of the conductor is increased, and the parameter value is restored to its initial value.
    Type: Grant
    Filed: March 14, 2002
    Date of Patent: February 17, 2004
    Assignee: Daro Semiconductors Ltd.
    Inventor: Eran Weis
  • Publication number: 20020133786
    Abstract: A method of designing a single-chip circuit system that includes several dissimilar (digital, analog, memory, power, RF, electro-optical) modules, and the system so designed. A prior art method is used for an initial design of the system, including signal and power conductors connecting the modules. Signal conductors are initially designed for current densities in a first range. Power conductors are initially designed for current densities in a second range. For each signal conductor, an initial value of a design parameter is changed to increase the current density into a higher third range, the resistance of the conductor is reduced, and the parameter value is restored to its initial value. For each power conductor, an initial value of a design parameter is changed to decrease the current density into a lower fourth range, the resistance of the conductor is increased, and the parameter value is restored to its initial value.
    Type: Application
    Filed: March 14, 2002
    Publication date: September 19, 2002
    Applicant: DARO SEMICONDUCTORS LTD.
    Inventor: Eran Weis