Patents by Inventor Erdem Matoglu
Erdem Matoglu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240055785Abstract: A cable assembly comprising a connector with a termination that enables high density and high signal integrity. Shields of cables are terminated to a paddle card via a conductive structure attached to a surface of the paddle card. The signal conductors of the cables are terminated to pads on the paddle card that are exposed within openings of the conductive structure. Such a structure creates a ground structure per cable that provides low insertion loss and low crosstalk, even when multiple cables are aligned side by side and terminated in one or more rows. The cables may be drainless, enabling a large number of cables, such as eight cables, to be packed within the width of a paddle card specified in high density standards such as QSFP-DD or OSFP. The cables may nonetheless have large diameter signal conductors, enabling 2.5 or 3 meter assemblies with less than 17 dB insertion loss.Type: ApplicationFiled: July 17, 2023Publication date: February 15, 2024Applicant: Amphenol CorporationInventors: Mark M. Ayzenberg, Khwajahussain Gadwal Mohammed, Erdem Matoglu, Catalin Muntean
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Patent number: 11705649Abstract: A cable assembly comprising a connector with a termination that enables high density and high signal integrity. Shields of cables are terminated to a paddle card via a conductive structure attached to a surface of the paddle card. The signal conductors of the cables are terminated to pads on the paddle card that are exposed within openings of the conductive structure. Such a structure creates a ground structure per cable that provides low insertion loss and low crosstalk, even when multiple cables are aligned side by side and terminated in one or more rows. The cables may be drainless, enabling a large number of cables, such as eight cables, to be packed within the width of a paddle card specified in high density standards such as QSFP-DD or OSFP. The cables may nonetheless have large diameter signal conductors, enabling 2.5 or 3 meter assemblies with less than 17 dB insertion loss.Type: GrantFiled: January 13, 2022Date of Patent: July 18, 2023Assignee: Amphenol CorporationInventors: Mark M. Ayzenberg, Khwajahussain Gadwal Mohammed, Erdem Matoglu, Catalin Muntean
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Publication number: 20220140505Abstract: A cable assembly comprising a connector with a termination that enables high density and high signal integrity. Shields of cables are terminated to a paddle card via a conductive structure attached to a surface of the paddle card. The signal conductors of the cables are terminated to pads on the paddle card that are exposed within openings of the conductive structure. Such a structure creates a ground structure per cable that provides low insertion loss and low crosstalk, even when multiple cables are aligned side by side and terminated in one or more rows. The cables may be drainless, enabling a large number of cables, such as eight cables, to be packed within the width of a paddle card specified in high density standards such as QSFP-DD or OSFP. The cables may nonetheless have large diameter signal conductors, enabling 2.5 or 3 meter assemblies with less than 17 dB insertion loss.Type: ApplicationFiled: January 13, 2022Publication date: May 5, 2022Applicant: Amphenol CorporationInventors: Mark M. Ayzenberg, Khwajahussain Gadwal Mohammed, Erdem Matoglu, Catalin Muntean
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Patent number: 11228123Abstract: A cable assembly comprising a connector with a termination that enables high density and high signal integrity. Shields of cables are terminated to a paddle card via a conductive structure attached to a surface of the paddle card. The signal conductors of the cables are terminated to pads on the paddle card that are exposed within openings of the conductive structure. Such a structure creates a ground structure per cable that provides low insertion loss and low crosstalk, even when multiple cables are aligned side by side and terminated in one or more rows. The cables may be drainless, enabling a large number of cables, such as eight cables, to be packed within the width of a paddle card specified in high density standards such as QSFP-DD or OSFP. The cables may nonetheless have large diameter signal conductors, enabling 2.5 or 3 meter assemblies with less than 17 dB insertion loss.Type: GrantFiled: December 16, 2019Date of Patent: January 18, 2022Assignee: Amphenol CorporationInventors: Mark M. Ayzenberg, Khwajahussain Gadwal Mohammed, Erdem Matoglu, Catalin Muntean
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Publication number: 20210167529Abstract: A cable assembly comprising a connector with a termination that enables high density and high signal integrity. Shields of cables are terminated to a paddle card via a conductive structure attached to a surface of the paddle card. The signal conductors of the cables are terminated to pads on the paddle card that are exposed within openings of the conductive structure. Such a structure creates a ground structure per cable that provides low insertion loss and low crosstalk, even when multiple cables are aligned side by side and terminated in one or more rows. The cables may be drainless, enabling a large number of cables, such as eight cables, to be packed within the width of a paddle card specified in high density standards such as QSFP-DD or OSFP. The cables may nonetheless have large diameter signal conductors, enabling 2.5 or 3 meter assemblies with less than 17 dB insertion loss.Type: ApplicationFiled: December 16, 2019Publication date: June 3, 2021Applicant: Amphenol CorporationInventors: Mark M. Ayzenberg, Khwajahussain Gadwal Mohammed, Erdem Matoglu, Catalin Muntean
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Publication number: 20200194911Abstract: A cable assembly comprising a connector with a termination that enables high density and high signal integrity. Shields of cables are terminated to a paddle card via a conductive structure attached to a surface of the paddle card. The signal conductors of the cables are terminated to pads on the paddle card that are exposed within openings of the conductive structure. Such a structure creates a ground structure per cable that provides low insertion loss and low crosstalk, even when multiple cables are aligned side by side and terminated in one or more rows. The cables may be drainless, enabling a large number of cables, such as eight cables, to be packed within the width of a paddle card specified in high density standards such as QSFP-DD or OSFP. The cables may nonetheless have large diameter signal conductors, enabling 2.5 or 3 meter assemblies with less than 17 dB insertion loss.Type: ApplicationFiled: December 16, 2019Publication date: June 18, 2020Applicant: Amphenol CorporationInventors: Mark M. Ayzenberg, Khwajahussain Gadwal Mohammed, Erdem Matoglu
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Patent number: 8390393Abstract: Embodiments of the present invention address deficiencies of the art in respect to via structure utilization in a PCB design and provide a novel and non-obvious method, system and computer program product for impedance discontinuity remediation for via stubs and connectors in a PCB. In one embodiment a method for impedance discontinuity remediation in a PCB can be provided. The method can include configuring a pre-distortion filter to negate an impedance discontinuity in an electrical signal caused by a transmission line with one of a via stub or a connector. The method further can include pre-distortion filtering an electrical signal before transmitting the electrical signal over the transmission line. Finally, the method can include transmitting the pre-distortion filtered electrical signal over the transmission line.Type: GrantFiled: September 4, 2012Date of Patent: March 5, 2013Assignee: International Business Machines CorporationInventors: Justin P. Bandholz, Moises Cases, Robert J. Christopher, Daniel de Araujo, Bradley D. Herrman, Erdem Matoglu, Bhyrav M. Mutnury, Pravin S. Patel, Nam H. Pham
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Publication number: 20120327622Abstract: Embodiments of the present invention address deficiencies of the art in respect to via structure utilization in a PCB design and provide a novel and non-obvious method, system and computer program product for impedance discontinuity remediation for via stubs and connectors in a PCB. In one embodiment a method for impedance discontinuity remediation in a PCB can be provided. The method can include configuring a pre-distortion filter to negate an impedance discontinuity in an electrical signal caused by a transmission line with one of a via stub or a connector. The method further can include pre-distortion filtering an electrical signal before transmitting the electrical signal over the transmission line. Finally, the method can include transmitting the pre-distortion filtered electrical signal over the transmission line.Type: ApplicationFiled: September 4, 2012Publication date: December 27, 2012Applicant: International Business Machines CorporationInventors: Justin P. Bandholz, Moises Cases, Robert J. Christopher, Daniel N. de Araujo, Bradley D. Herrman, Erdem Matoglu, Bhyrav M. Mutnury, Pravin S. Patel, Nam H. Pham
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Patent number: 8289101Abstract: Embodiments of the present invention address deficiencies of the art in respect to via structure utilization in a PCB design and provide a novel and non-obvious method, system and computer program product for impedance discontinuity remediation for via stubs and connectors in a PCB. In one embodiment a method for impedance discontinuity remediation in a PCB can be provided. The method can include configuring a pre-distortion filter to negate an impedance discontinuity in an electrical signal caused by a transmission line with one of a via stub or a connector. The method further can include pre-distortion filtering an electrical signal before transmitting the electrical signal over the transmission line. Finally, the method can include transmitting the pre-distortion filtered electrical signal over the transmission line.Type: GrantFiled: April 19, 2007Date of Patent: October 16, 2012Assignee: International Business Machines CorporationInventors: Justin P. Bandholz, Moises Cases, Robert J. Christopher, Daniel N. de Araujo, Bradley D. Herrman, Erdem Matoglu, Bhyrav M. Mutnury, Pravin S. Patel, Nam H. Pham
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Patent number: 8084692Abstract: An apparatus having reduced noise coupling includes a core layer having an upper and lower surface, the upper and lower surface each including a copper sheet layer, a pre-preg layer having an upper surface and a lower surface, the upper surface of the pre-preg layer coupled to the lower surface of the core layer, a core insulating layer having an upper surface and a lower surface, the upper surface of the core insulating layer coupled to the lower surface of the pre-preg layer, a return current reference layer disposed on the lower surface of the core insulator layer and high-speed signal traces disposed on the upper surface of the core insulating layer, each of the high speed signal traces disposed on a pedestal defined by a section of the pre-preg layer and the core insulating layer, each pedestal being separated by an air gap disposed between adjacent pedestals.Type: GrantFiled: October 25, 2007Date of Patent: December 27, 2011Assignee: International Business Machines CorporationInventors: Moises Cases, Bradley D. Herrman, Kent B. Howieson, Erdem Matoglu, Bhyrav M. Mutnury, Pravin S. Patel, Nam H. Pham, Caleb J. Wesley
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Patent number: 7813447Abstract: An apparatus, system, and method are disclosed for dynamic phase equalization in a communication channel. A transmitter history module stores a plurality of bits from a data stream that is transmitted through the communication channel. A transmitter detection module detects a pre-transition bit of a first value that is preceded in the data stream by at least one bit of the first value and followed by a transition bit with a second value. A driver module transmits the data stream by driving the communication channel. A transition module pre-drives the communication channel to the second voltage of the transition bit during a bit time interval of the pre-transition bit.Type: GrantFiled: November 15, 2006Date of Patent: October 12, 2010Assignee: International Business Machines CorporationInventors: Daniel N. De Araujo, Moises Cases, Bradley D. Herrman, Erdem Matoglu, Bhyrav M. Mutnury, Pravin S. Patel, Nam H. Pham
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Patent number: 7759958Abstract: An apparatus, system, and method are disclosed for integrating component testing. A voltage module modifies a reference voltage integral to an electronic device to a plurality of reference voltage values. A test module tests a component of the electronic device at each of the plurality of reference voltage values. In addition, the test module determines a voltage range for the component, wherein the voltage range comprises voltage values between a high voltage failure and a low voltage failure. An optimization module sets the reference voltage value to within the voltage range.Type: GrantFiled: September 21, 2007Date of Patent: July 20, 2010Assignee: International Business Machines CorporationInventors: Moises Cases, Shiva R. Dasari, Erdem Matoglu, Bhyrav M. Mutnury, Nam H. Pham
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Patent number: 7725783Abstract: The present invention assesses memory (DIMM) strength by calculating frequency content of a radiated field which is collected by an apparatus, such as a dipole antenna. Radiated field is created by accelerated charge, which is a function of the slew rate or DIMM strength. Radiated power is directly proportional to the frequency at which bits are driven. By separating the radiated field from the near field or stored field, the DIMM strength content is isolated from other functional DIMM issues, such as tRCD latency, refresh cycles, addressing mode, etc. By examining the radiated power, the disadvantages of the prior art, such as by probing the DIMM's contacts, are avoided.Type: GrantFiled: July 20, 2007Date of Patent: May 25, 2010Assignee: International Business Machines CorporationInventors: Moises Cases, Daniel N. de Araujo, Bradley D. Herrman, Erdem Matoglu, Bhyrav M. Mutnury, Pravin Patel, Nam H. Pham
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Patent number: 7701222Abstract: A method for testing a printed circuit board to determining the dielectric loss associated with the circuit board material relative to a standard. Dielectric losses in the material generate heat when a high frequency electronic signal, such as a microwave frequency signal, is communicated through a microstrip that is embedded within the printed circuit board. The temperature or spectrum at the surface of printed circuit board is measured and compared against the temperature or spectrum of the standard to determine whether the material under test is acceptable. While various temperature measurement devices may be used, the temperature is preferably measured without contacting the surface, such as using an infrared radiation probe.Type: GrantFiled: October 19, 2007Date of Patent: April 20, 2010Assignee: International Business Machines CorporationInventors: Moises Cases, Bradley Donald Herrman, Kent Barclay Howieson, Erdem Matoglu, Bhyrav Murthy Mutnury, Pravin Patel, Nam Huu Pham, Caleb James Wesley
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Patent number: 7533458Abstract: Methods and systems for reducing noise coupling in high-speed digital systems. Exemplary embodiments include a method, including etching a plurality of high speed signal traces onto a core insulating layer, forming trenches on respective sides of the plurality of high speed signal traces, thereby removing insulating material adjacent to the plurality of high speed signal traces and forming pedestals having remaining insulating material, the plurality of high speed signal traces disposed on and coupled to the remaining insulating material, coupling pre-preg material on the high speed signal traces, removing the pre-preg material adjacent the trenches, thereby retaining the pre-preg material aligned with the high speed signal traces, and heating and pressing a core layer to the pre-preg layer, and heating and pressing the pre-preg layer to the core insulating layer.Type: GrantFiled: July 17, 2008Date of Patent: May 19, 2009Assignee: International Business Machines CorporationInventors: Moises Cases, Bradley D. Herrman, Kent B. Howieson, Erdem Matoglu, Bhyrav M. Mutnury, Pravin S. Patel, Nam H. Pham, Caleb J. Wesley
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Publication number: 20090107705Abstract: Methods and systems for reducing noise coupling in high-speed digital systems. Exemplary embodiments include a method, including etching a plurality of high speed signal traces onto a core insulating layer, forming trenches on respective sides of the plurality of high speed signal traces, thereby removing insulating material adjacent to the plurality of high speed signal traces and forming pedestals having remaining insulating material, the plurality of high speed signal traces disposed on and coupled to the remaining insulating material, coupling pre-preg material on the high speed signal traces, removing the pre-preg material adjacent the trenches, thereby retaining the pre-preg material aligned with the high speed signal traces, and heating and pressing a core layer to the pre-preg layer, and heating and pressing the pre-preg layer to the core insulating layer.Type: ApplicationFiled: October 25, 2007Publication date: April 30, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Moises Cases, Bradley D. Herrman, Kent B. Howieson, Erdem Matoglu, Bhyrav M. Mutnury, Pravin S. Patel, Nam H. Pham, Caleb J. Wesley
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Publication number: 20090106976Abstract: Methods and systems for reducing noise coupling in high-speed digital systems. Exemplary embodiments include a method, including etching a plurality of high speed signal traces onto a core insulating layer, forming trenches on respective sides of the plurality of high speed signal traces, thereby removing insulating material adjacent to the plurality of high speed signal traces and forming pedestals having remaining insulating material, the plurality of high speed signal traces disposed on and coupled to the remaining insulating material, coupling pre-preg material on the high speed signal traces, removing the pre-preg material adjacent the trenches, thereby retaining the pre-preg material aligned with the high speed signal traces, and heating and pressing a core layer to the pre-preg layer, and heating and pressing the pre-preg layer to the core insulating layer.Type: ApplicationFiled: July 17, 2008Publication date: April 30, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Moises Cases, Bradley D. Herrman, Kent B. Howieson, Erdem Matoglu, Bhyrav M. Mutnury, Pravin S. Patel, Nam H. Pham, Caleb J. Wesley
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Publication number: 20090102487Abstract: A method for testing a printed circuit board to determining the dielectric loss associated with the circuit board material relative to a standard. Dielectric losses in the material generate heat when a high frequency electronic signal, such as a microwave frequency signal, is communicated through a microstrip that is embedded within the printed circuit board. The temperature or spectrum at the surface of printed circuit board is measured and compared against the temperature or spectrum of the standard to determine whether the material under test is acceptable. While various temperature measurement devices may be used, the temperature is preferably measured without contacting the surface, such as using an infrared radiation probe.Type: ApplicationFiled: October 19, 2007Publication date: April 23, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Moises Cases, Bradley Donald Herrman, Kent Barclay Howieson, Erdem Matoglu, Bhyrav Murthy Mutnury, Pravin Patel, Nam Huu Pham, Celeb James Wesley
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Publication number: 20090079456Abstract: An apparatus, system, and method are disclosed for integrating component testing. A voltage module modifies a reference voltage integral to an electronic device to a plurality of reference voltage values. A test module tests a component of the electronic device at each of the plurality of reference voltage values. In addition, the test module determines a voltage range for the component, wherein the voltage range comprises voltage values between a high voltage failure and a low voltage failure. An optimization module sets the reference voltage value to within the voltage range.Type: ApplicationFiled: September 21, 2007Publication date: March 26, 2009Applicant: International Business Machines CorporationInventors: Moises Cases, Shiva R. Dasari, Erdem Matoglu, Bhyrav Murthy Mutnury, Nam Huu Pham
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Publication number: 20090049414Abstract: Reducing via stub resonance in printed circuit boards. In one aspect, a method for reducing via stub resonance in a circuit board includes determining that resonance exists for a signal to be transmitted through a signal via extending across a plurality of layers in the circuit board. The resonance is caused by a via stub of the signal via, the via stub extending past a layer connected to the signal via. A location is determined for a ground via to be placed relative to the signal via, the location of the ground via being determined based on reducing the resonance for the signal to be transmitted in the signal via.Type: ApplicationFiled: August 16, 2007Publication date: February 19, 2009Applicant: International Business Machines CorporationInventors: Bhyrav M. MUTNURY, Moises Cases, Wallace G. Tuten, Erdem Matoglu