Abstract: A hermetically sealed, surface mount chip carrier for a semiconductor device is disclosed. The chip carrier is formed of a plurality of layers of conductive material and insulating material. A cavity adapted to receive the semiconductor device is provided within the layers. The device is electrically connected to the conductive layers via electrical conductors bonded to exposed surfaces or shelves on selected ones of the conductive layers. The layers have a continuous periphery to eliminate gaps or vertical discontiniuties in the chip carrier. The conductive and insulating layers have similar coefficients of thermal expansion to provide unitary expansion and contraction of the entire carrier so as to maintain a hermetic seal in the chip carrier when subjected to thermal stresses.