Patents by Inventor Erez Barak
Erez Barak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11074184Abstract: Methods, systems and computer program products for monitoring delivered packages are provided. Aspects include receiving, by a co-processor, a data stream and performing processing on the data stream. Aspects also include writing, by the co-processor, a data record into the output buffer. Based on a determination that the data record should replace a most recently stored data record in a cache, aspects include providing, by the co-processor to the cache controller, an instruction for the cache controller to write the data record to a location in the cache obtained from a most recently used address register. Based on a determination that the data record should not replace the most recently stored data record in the cache, aspects include writing, by the cache controller, the data record to an available location in the cache.Type: GrantFiled: April 15, 2019Date of Patent: July 27, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael Cadigan, Jr., Erez Barak, Deepankar Bhattacharjee, Yair Fried, Jonathan Hsieh, Martin Recktenwald, Aditya Nitin Puranik
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Publication number: 20200327059Abstract: Methods, systems and computer program products for monitoring delivered packages are provided. Aspects include receiving, by a co-processor, a data stream and performing processing on the data stream. Aspects also include writing, by the co-processor, a data record into the output buffer. Based on a determination that the data record should replace a most recently stored data record in a cache, aspects include providing, by the co-processor to the cache controller, an instruction for the cache controller to write the data record to a location in the cache obtained from a most recently used address register. Based on a determination that the data record should not replace the most recently stored data record in the cache, aspects include writing, by the cache controller, the data record to an available location in the cache.Type: ApplicationFiled: April 15, 2019Publication date: October 15, 2020Inventors: MICHAEL CADIGAN, JR., EREZ BARAK, DEEPANKAR BHATTACHARJEE, YAIR FRIED, JONATHAN HSIEH, MARTIN RECKTENWALD, ADITYA NITIN PURANIK
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Patent number: 10614183Abstract: The present disclosure provides reducing clock power consumption of a computer processor by simulating, in a baseline simulation of a computer processor design using a software model of the computer processor design, performance of an instruction by the computer processor design, to produce a baseline result of the instruction, and identifying a circuit of the computer processor design that receives a clock signal during performance of the instruction, and in a comparison simulation of the computer processor design using the software model of the computer processor design, simulating performance of the instruction by the computer processor design while injecting a corruption signal into the circuit, to produce a comparison result of the instruction, and designating the circuit for clock gating when processing the instruction, if the comparison result of the instruction is identical to the baseline result of the instruction.Type: GrantFiled: December 29, 2017Date of Patent: April 7, 2020Assignee: International Business Machines CorporationInventors: Erez Barak, Giora Biran, Amir Turi, Osher Yifrach
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Patent number: 10606971Abstract: Examples of techniques for modifying testing tools are described herein. An example computer-implemented method includes receiving, via a processor, a netlist comprising a complex coverage event that depends on a singular independent signal. The method includes detecting, via the processor, that complex coverage event can be separated into the singular independent signal and a logic state based on a structural logic analysis. The method also includes modifying, via the processor, a testing tool to test the netlist based on the singular independent signal.Type: GrantFiled: November 29, 2017Date of Patent: March 31, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Erez Barak, Shlomit Koyfman, Shiri Moran, Ido Rozenberg, Osher Yifrach
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Patent number: 10585995Abstract: Reducing clock power consumption of a computer processor by simulating, in a baseline simulation of a computer processor design using a software model of the computer processor design, performance of an instruction by the computer processor design, to produce a baseline result of the instruction, and identifying a circuit of the computer processor design that receives a clock signal during performance of the instruction, and in a comparison simulation of the computer processor design using the software model of the computer processor design, simulating performance of the instruction by the computer processor design while injecting a corruption signal into the circuit, to produce a comparison result of the instruction, and designating the circuit for clock gating when processing the instruction, if the comparison result of the instruction is identical to the baseline result of the instruction.Type: GrantFiled: June 26, 2017Date of Patent: March 10, 2020Assignee: International Business Machines CorporationInventors: Erez Barak, Giora Biran, Amir Turi, Osher Yifrach
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Patent number: 10572624Abstract: A computer-implemented method, computerized apparatus and computer program product for modified design debugging using differential trace back. An indication of an interface signal in a time unit in an execution resulting in a value miscompare between a design and a modification thereof is obtained. For each of the design and the modification, a data record detailing each signal value in each time unit, and a structure description detailing all components and interconnections thereamong, are obtained. A suspect root cause of the value miscompare is traced back from the interface signal in the time unit, the tracing back comprising comparing values in the data records of candidate signals selected based on the data records and the structure descriptions.Type: GrantFiled: April 30, 2018Date of Patent: February 25, 2020Assignee: International Business Machines CorporationInventors: Erez Barak, Shlomit Koyfman, Eyal Naor, Ziv Nevo, Osher Yifrach
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Publication number: 20190332741Abstract: A computer-implemented method, computerized apparatus and computer program product for modified design debugging using differential trace back. An indication of an interface signal in a time unit in an execution resulting in a value miscompare between a design and a modification thereof is obtained. For each of the design and the modification, a data record detailing each signal value in each time unit, and a structure description detailing all components and interconnections thereamong, are obtained. A suspect root cause of the value miscompare is traced back from the interface signal in the time unit, the tracing back comprising comparing values in the data records of candidate signals selected based on the data records and the structure descriptions.Type: ApplicationFiled: April 30, 2018Publication date: October 31, 2019Inventors: EREZ BARAK, Shlomit Koyfman, Eyal Naor, Ziv Nevo, Osher Yifrach
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Patent number: 10324816Abstract: Checking a computer processor design for soft error handling. A baseline simulation of a computer processor design is monitored to identify a target processing cycle of the baseline simulation during which a predefined event occurs during the baseline simulation. The baseline simulation is performed in accordance with a software model of the computer processor design, and the event is associated with processing an instruction that directly involves a predefined error injection target. A test simulation of the computer processor design is performed in accordance with the software model of the computer processor design. An error is injected into the predefined error injection target during a target processing cycle of the test simulation. A determination is made as to whether the error is detected by error-checking logic of the computer processor design.Type: GrantFiled: March 8, 2017Date of Patent: June 18, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Erez Barak, Nicol Hofmann, Cédric Lichtenau, Osher Yifrach
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Patent number: 10324815Abstract: Error checking for a computer processor design under test. In multiple processing threads, and in accordance with a hardware model of a computer processor design under test, the instructions of multiple instruction sequences corresponding to the processing threads are processed, thereby resulting in an order in which the instructions are processed in accordance with the hardware model, and producing an actual result for each of the instructions. An expected result is determined for any of the instructions in accordance with a reference model of the computer processor design under test and in accordance with the order in which the instructions were processed in accordance with the hardware model. Any of the instructions whose expected result and actual result differ are identified.Type: GrantFiled: February 14, 2017Date of Patent: June 18, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Erez Barak, Oz D. Hershkovitz, Gilad Merran, Eyal Naor
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Patent number: 10318395Abstract: Checking a computer processor design for soft error handling. A baseline simulation of a computer processor design is monitored to identify a target processing cycle of the baseline simulation during which a predefined event occurs during the baseline simulation. The baseline simulation is performed in accordance with a software model of the computer processor design, and the event is associated with processing an instruction that directly involves a predefined error injection target. A test simulation of the computer processor design is performed in accordance with the software model of the computer processor design. An error is injected into the predefined error injection target during a target processing cycle of the test simulation. A determination is made as to whether the error is detected by error-checking logic of the computer processor design.Type: GrantFiled: November 13, 2017Date of Patent: June 11, 2019Assignee: INTERNATION BUSINESS MACHINES CORPORATIONInventors: Erez Barak, Nicol Hofmann, Cédric Lichtenau, Osher Yifrach
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Patent number: 10310936Abstract: Embodiments include a method for temporary pipeline marking for processor error workarounds. The method includes monitoring an execution unit pipeline of a processor for an event associated with a programmable instruction operational code that is predetermined to cause a stuck state resulting in an errant instruction execution. The execution unit pipeline is marked for a workaround action based on detecting the event. A clearing action is triggered based on the marking, where the triggering is conditionally triggered by a next instruction in the execution unit pipeline having a same instruction type as the programmable instruction operational code. The marking of the pipeline is cleared based on the triggering of the clearing action, where the clearing action is a subsequent pipeline flush event based on the next instruction having the same instruction type reaching a same pipeline stage that results in a stuck state prior to completion of the next instruction.Type: GrantFiled: January 12, 2017Date of Patent: June 4, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Erez Barak, Steven R. Carlough, Eyal Gonen, Juergen Haess, Silvia M. Mueller
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Publication number: 20190163600Abstract: Examples of techniques for modifying testing tools are described herein. An example computer-implemented method includes receiving, via a processor, a netlist comprising a complex coverage event that depends on a singular independent signal. The method includes detecting, via the processor, that complex coverage event can be separated into the singular independent signal and a logic state based on a structural logic analysis. The method also includes modifying, via the processor, a testing tool to test the netlist based on the singular independent signal.Type: ApplicationFiled: November 29, 2017Publication date: May 30, 2019Inventors: EREZ BARAK, SHLOMIT KOYFMAN, SHIRI MORAN, IDO ROZENBERG, OSHER YIFRACH
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Patent number: 10296687Abstract: The present disclosure provides reducing clock power consumption of a computer processor by simulating, in a baseline simulation of a computer processor design using a software model of the computer processor design, performance of an instruction by the computer processor design, to produce a baseline result of the instruction, and identifying a circuit of the computer processor design that receives a clock signal during performance of the instruction, and in a comparison simulation of the computer processor design using the software model of the computer processor design, simulating performance of the instruction by the computer processor design while injecting a corruption signal into the circuit, to produce a comparison result of the instruction, and designating the circuit for clock gating when processing the instruction, if the comparison result of the instruction is identical to the baseline result of the instruction.Type: GrantFiled: February 23, 2018Date of Patent: May 21, 2019Assignee: International Business Machines CorporationInventors: Erez Barak, Giora Biran, Amir Turi, Osher Yifrach
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Publication number: 20180373611Abstract: The present disclosure provides reducing clock power consumption of a computer processor by simulating, in a baseline simulation of a computer processor design using a software model of the computer processor design, performance of an instruction by the computer processor design, to produce a baseline result of the instruction, and identifying a circuit of the computer processor design that receives a clock signal during performance of the instruction, and in a comparison simulation of the computer processor design using the software model of the computer processor design, simulating performance of the instruction by the computer processor design while injecting a corruption signal into the circuit, to produce a comparison result of the instruction, and designating the circuit for clock gating when processing the instruction, if the comparison result of the instruction is identical to the baseline result of the instruction.Type: ApplicationFiled: December 29, 2017Publication date: December 27, 2018Inventors: Erez Barak, Giora Biran, Amir Turi, Osher Yifrach
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Publication number: 20180373610Abstract: Reducing clock power consumption of a computer processor by simulating, in a baseline simulation of a computer processor design using a software model of the computer processor design, performance of an instruction by the computer processor design, to produce a baseline result of the instruction, and identifying a circuit of the computer processor design that receives a clock signal during performance of the instruction, and in a comparison simulation of the computer processor design using the software model of the computer processor design, simulating performance of the instruction by the computer processor design while injecting a corruption signal into the circuit, to produce a comparison result of the instruction, and designating the circuit for clock gating when processing the instruction, if the comparison result of the instruction is identical to the baseline result of the instruction.Type: ApplicationFiled: June 26, 2017Publication date: December 27, 2018Inventors: Erez Barak, Giora Biran, Amir Turi, Osher Yifrach
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Publication number: 20180373828Abstract: The present disclosure provides reducing clock power consumption of a computer processor by simulating, in a baseline simulation of a computer processor design using a software model of the computer processor design, performance of an instruction by the computer processor design, to produce a baseline result of the instruction, and identifying a circuit of the computer processor design that receives a clock signal during performance of the instruction, and in a comparison simulation of the computer processor design using the software model of the computer processor design, simulating performance of the instruction by the computer processor design while injecting a corruption signal into the circuit, to produce a comparison result of the instruction, and designating the circuit for clock gating when processing the instruction, if the comparison result of the instruction is identical to the baseline result of the instruction.Type: ApplicationFiled: February 23, 2018Publication date: December 27, 2018Inventors: Erez Barak, Giora Biran, Amir Turi, Osher Yifrach
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Publication number: 20180260308Abstract: Checking a computer processor design for soft error handling. A baseline simulation of a computer processor design is monitored to identify a target processing cycle of the baseline simulation during which a predefined event occurs during the baseline simulation. The baseline simulation is performed in accordance with a software model of the computer processor design, and the event is associated with processing an instruction that directly involves a predefined error injection target. A test simulation of the computer processor design is performed in accordance with the software model of the computer processor design. An error is injected into the predefined error injection target during a target processing cycle of the test simulation. A determination is made as to whether the error is detected by error-checking logic of the computer processor design.Type: ApplicationFiled: March 8, 2017Publication date: September 13, 2018Inventors: Erez Barak, Nicol Hofmann, Cédric Lichtenau, Osher Yifrach
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Publication number: 20180260311Abstract: Checking a computer processor design for soft error handling. A baseline simulation of a computer processor design is monitored to identify a target processing cycle of the baseline simulation during which a predefined event occurs during the baseline simulation. The baseline simulation is performed in accordance with a software model of the computer processor design, and the event is associated with processing an instruction that directly involves a predefined error injection target. A test simulation of the computer processor design is performed in accordance with the software model of the computer processor design. An error is injected into the predefined error injection target during a target processing cycle of the test simulation. A determination is made as to whether the error is detected by error-checking logic of the computer processor design.Type: ApplicationFiled: November 13, 2017Publication date: September 13, 2018Inventors: Erez Barak, Nicol Hofmann, Cédric Lichtenau, Osher Yifrach
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Publication number: 20180232292Abstract: Error checking for a computer processor design under test. In multiple processing threads, and in accordance with a hardware model of a computer processor design under test, the instructions of multiple instruction sequences corresponding to the processing threads are processed, thereby resulting in an order in which the instructions are processed in accordance with the hardware model, and producing an actual result for each of the instructions. An expected result is determined for any of the instructions in accordance with a reference model of the computer processor design under test and in accordance with the order in which the instructions were processed in accordance with the hardware model. Any of the instructions whose expected result and actual result differ are identified.Type: ApplicationFiled: February 14, 2017Publication date: August 16, 2018Inventors: Erez Barak, Oz D. Hershkovitz, Gilad Merran, Eyal Naor
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Patent number: 9760909Abstract: Techniques for generating marketing lead intelligence information are described. Some embodiments provide a marketing activity support system (“MASS”) configured to generate lead intelligence by aggregating marketing activity information and customer information. In one embodiment, the MASS transmits a marketing message that references a Web page or other marketing content. Next, the MASS receives tracking information about activities of a customer with respect to the referenced Web page. The MASS then generates lead intelligence information about the customer by aggregating the tracking information, personal information about the customer, and/or information about an associated marketing campaign. The MASS may then present the generated lead intelligence information, such as by displaying details about the customer and their activities with respect to the Web page.Type: GrantFiled: October 26, 2016Date of Patent: September 12, 2017Assignee: Marketo, Inc.Inventors: Erez Barak, Brian Scott Goffman