Patents by Inventor Erez Barak

Erez Barak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10324816
    Abstract: Checking a computer processor design for soft error handling. A baseline simulation of a computer processor design is monitored to identify a target processing cycle of the baseline simulation during which a predefined event occurs during the baseline simulation. The baseline simulation is performed in accordance with a software model of the computer processor design, and the event is associated with processing an instruction that directly involves a predefined error injection target. A test simulation of the computer processor design is performed in accordance with the software model of the computer processor design. An error is injected into the predefined error injection target during a target processing cycle of the test simulation. A determination is made as to whether the error is detected by error-checking logic of the computer processor design.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: June 18, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Erez Barak, Nicol Hofmann, Cédric Lichtenau, Osher Yifrach
  • Patent number: 10324815
    Abstract: Error checking for a computer processor design under test. In multiple processing threads, and in accordance with a hardware model of a computer processor design under test, the instructions of multiple instruction sequences corresponding to the processing threads are processed, thereby resulting in an order in which the instructions are processed in accordance with the hardware model, and producing an actual result for each of the instructions. An expected result is determined for any of the instructions in accordance with a reference model of the computer processor design under test and in accordance with the order in which the instructions were processed in accordance with the hardware model. Any of the instructions whose expected result and actual result differ are identified.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: June 18, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Erez Barak, Oz D. Hershkovitz, Gilad Merran, Eyal Naor
  • Patent number: 10318395
    Abstract: Checking a computer processor design for soft error handling. A baseline simulation of a computer processor design is monitored to identify a target processing cycle of the baseline simulation during which a predefined event occurs during the baseline simulation. The baseline simulation is performed in accordance with a software model of the computer processor design, and the event is associated with processing an instruction that directly involves a predefined error injection target. A test simulation of the computer processor design is performed in accordance with the software model of the computer processor design. An error is injected into the predefined error injection target during a target processing cycle of the test simulation. A determination is made as to whether the error is detected by error-checking logic of the computer processor design.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: June 11, 2019
    Assignee: INTERNATION BUSINESS MACHINES CORPORATION
    Inventors: Erez Barak, Nicol Hofmann, Cédric Lichtenau, Osher Yifrach
  • Patent number: 10310936
    Abstract: Embodiments include a method for temporary pipeline marking for processor error workarounds. The method includes monitoring an execution unit pipeline of a processor for an event associated with a programmable instruction operational code that is predetermined to cause a stuck state resulting in an errant instruction execution. The execution unit pipeline is marked for a workaround action based on detecting the event. A clearing action is triggered based on the marking, where the triggering is conditionally triggered by a next instruction in the execution unit pipeline having a same instruction type as the programmable instruction operational code. The marking of the pipeline is cleared based on the triggering of the clearing action, where the clearing action is a subsequent pipeline flush event based on the next instruction having the same instruction type reaching a same pipeline stage that results in a stuck state prior to completion of the next instruction.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: June 4, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Erez Barak, Steven R. Carlough, Eyal Gonen, Juergen Haess, Silvia M. Mueller
  • Publication number: 20190163600
    Abstract: Examples of techniques for modifying testing tools are described herein. An example computer-implemented method includes receiving, via a processor, a netlist comprising a complex coverage event that depends on a singular independent signal. The method includes detecting, via the processor, that complex coverage event can be separated into the singular independent signal and a logic state based on a structural logic analysis. The method also includes modifying, via the processor, a testing tool to test the netlist based on the singular independent signal.
    Type: Application
    Filed: November 29, 2017
    Publication date: May 30, 2019
    Inventors: EREZ BARAK, SHLOMIT KOYFMAN, SHIRI MORAN, IDO ROZENBERG, OSHER YIFRACH
  • Patent number: 10296687
    Abstract: The present disclosure provides reducing clock power consumption of a computer processor by simulating, in a baseline simulation of a computer processor design using a software model of the computer processor design, performance of an instruction by the computer processor design, to produce a baseline result of the instruction, and identifying a circuit of the computer processor design that receives a clock signal during performance of the instruction, and in a comparison simulation of the computer processor design using the software model of the computer processor design, simulating performance of the instruction by the computer processor design while injecting a corruption signal into the circuit, to produce a comparison result of the instruction, and designating the circuit for clock gating when processing the instruction, if the comparison result of the instruction is identical to the baseline result of the instruction.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: May 21, 2019
    Assignee: International Business Machines Corporation
    Inventors: Erez Barak, Giora Biran, Amir Turi, Osher Yifrach
  • Publication number: 20180373828
    Abstract: The present disclosure provides reducing clock power consumption of a computer processor by simulating, in a baseline simulation of a computer processor design using a software model of the computer processor design, performance of an instruction by the computer processor design, to produce a baseline result of the instruction, and identifying a circuit of the computer processor design that receives a clock signal during performance of the instruction, and in a comparison simulation of the computer processor design using the software model of the computer processor design, simulating performance of the instruction by the computer processor design while injecting a corruption signal into the circuit, to produce a comparison result of the instruction, and designating the circuit for clock gating when processing the instruction, if the comparison result of the instruction is identical to the baseline result of the instruction.
    Type: Application
    Filed: February 23, 2018
    Publication date: December 27, 2018
    Inventors: Erez Barak, Giora Biran, Amir Turi, Osher Yifrach
  • Publication number: 20180373610
    Abstract: Reducing clock power consumption of a computer processor by simulating, in a baseline simulation of a computer processor design using a software model of the computer processor design, performance of an instruction by the computer processor design, to produce a baseline result of the instruction, and identifying a circuit of the computer processor design that receives a clock signal during performance of the instruction, and in a comparison simulation of the computer processor design using the software model of the computer processor design, simulating performance of the instruction by the computer processor design while injecting a corruption signal into the circuit, to produce a comparison result of the instruction, and designating the circuit for clock gating when processing the instruction, if the comparison result of the instruction is identical to the baseline result of the instruction.
    Type: Application
    Filed: June 26, 2017
    Publication date: December 27, 2018
    Inventors: Erez Barak, Giora Biran, Amir Turi, Osher Yifrach
  • Publication number: 20180373611
    Abstract: The present disclosure provides reducing clock power consumption of a computer processor by simulating, in a baseline simulation of a computer processor design using a software model of the computer processor design, performance of an instruction by the computer processor design, to produce a baseline result of the instruction, and identifying a circuit of the computer processor design that receives a clock signal during performance of the instruction, and in a comparison simulation of the computer processor design using the software model of the computer processor design, simulating performance of the instruction by the computer processor design while injecting a corruption signal into the circuit, to produce a comparison result of the instruction, and designating the circuit for clock gating when processing the instruction, if the comparison result of the instruction is identical to the baseline result of the instruction.
    Type: Application
    Filed: December 29, 2017
    Publication date: December 27, 2018
    Inventors: Erez Barak, Giora Biran, Amir Turi, Osher Yifrach
  • Publication number: 20180260308
    Abstract: Checking a computer processor design for soft error handling. A baseline simulation of a computer processor design is monitored to identify a target processing cycle of the baseline simulation during which a predefined event occurs during the baseline simulation. The baseline simulation is performed in accordance with a software model of the computer processor design, and the event is associated with processing an instruction that directly involves a predefined error injection target. A test simulation of the computer processor design is performed in accordance with the software model of the computer processor design. An error is injected into the predefined error injection target during a target processing cycle of the test simulation. A determination is made as to whether the error is detected by error-checking logic of the computer processor design.
    Type: Application
    Filed: March 8, 2017
    Publication date: September 13, 2018
    Inventors: Erez Barak, Nicol Hofmann, Cédric Lichtenau, Osher Yifrach
  • Publication number: 20180260311
    Abstract: Checking a computer processor design for soft error handling. A baseline simulation of a computer processor design is monitored to identify a target processing cycle of the baseline simulation during which a predefined event occurs during the baseline simulation. The baseline simulation is performed in accordance with a software model of the computer processor design, and the event is associated with processing an instruction that directly involves a predefined error injection target. A test simulation of the computer processor design is performed in accordance with the software model of the computer processor design. An error is injected into the predefined error injection target during a target processing cycle of the test simulation. A determination is made as to whether the error is detected by error-checking logic of the computer processor design.
    Type: Application
    Filed: November 13, 2017
    Publication date: September 13, 2018
    Inventors: Erez Barak, Nicol Hofmann, Cédric Lichtenau, Osher Yifrach
  • Publication number: 20180232292
    Abstract: Error checking for a computer processor design under test. In multiple processing threads, and in accordance with a hardware model of a computer processor design under test, the instructions of multiple instruction sequences corresponding to the processing threads are processed, thereby resulting in an order in which the instructions are processed in accordance with the hardware model, and producing an actual result for each of the instructions. An expected result is determined for any of the instructions in accordance with a reference model of the computer processor design under test and in accordance with the order in which the instructions were processed in accordance with the hardware model. Any of the instructions whose expected result and actual result differ are identified.
    Type: Application
    Filed: February 14, 2017
    Publication date: August 16, 2018
    Inventors: Erez Barak, Oz D. Hershkovitz, Gilad Merran, Eyal Naor
  • Patent number: 9760909
    Abstract: Techniques for generating marketing lead intelligence information are described. Some embodiments provide a marketing activity support system (“MASS”) configured to generate lead intelligence by aggregating marketing activity information and customer information. In one embodiment, the MASS transmits a marketing message that references a Web page or other marketing content. Next, the MASS receives tracking information about activities of a customer with respect to the referenced Web page. The MASS then generates lead intelligence information about the customer by aggregating the tracking information, personal information about the customer, and/or information about an associated marketing campaign. The MASS may then present the generated lead intelligence information, such as by displaying details about the customer and their activities with respect to the Web page.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: September 12, 2017
    Assignee: Marketo, Inc.
    Inventors: Erez Barak, Brian Scott Goffman
  • Publication number: 20170123924
    Abstract: Embodiments include a method for temporary pipeline marking for processor error workarounds. The method includes monitoring an execution unit pipeline of a processor for an event associated with a programmable instruction operational code that is predetermined to cause a stuck state resulting in an errant instruction execution. The execution unit pipeline is marked for a workaround action based on detecting the event. A clearing action is triggered based on the marking, where the triggering is conditionally triggered by a next instruction in the execution unit pipeline having a same instruction type as the programmable instruction operational code. The marking of the pipeline is cleared based on the triggering of the clearing action, where the clearing action is a subsequent pipeline flush event based on the next instruction having the same instruction type reaching a same pipeline stage that results in a stuck state prior to completion of the next instruction.
    Type: Application
    Filed: January 12, 2017
    Publication date: May 4, 2017
    Inventors: Erez Barak, Steven R. Carlough, Eyal Gonen, Juergen Haess, Silvia M. Mueller
  • Patent number: 9600616
    Abstract: A computer-implemented method may include retrieving a design netlist with a processor, identifying, via the processor, a logic structure in the design netlist, generating, via the processor, a driver based on the logic structure, applying, via the processor, a simulation and a formal model based on the driver, and testing, via the processor, an output of the simulation and the formal model.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: March 21, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Eli Arbel, Erez Barak, Bodo Hoppe, Udo Krautz, Shiri Moran
  • Patent number: 9588852
    Abstract: Embodiments include a method for temporary pipeline marking for processor error workarounds. The method includes monitoring a pipeline of a processor for an event that is predetermined to place the processor in a stuck state that results in an errant instruction execution result due to the stuck state or repeated resource contention causing performance degradation. The pipeline is marked for a workaround action based on detecting the event. A clearing action is triggered based on the marking of the pipeline. The marking of the pipeline is cleared based on the triggering of the clearing action.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: March 7, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Erez Barak, Steven R. Carlough, Eyal Gonen, Juergen Haess, Silvia M. Mueller
  • Patent number: 9575836
    Abstract: Embodiments include a computer system for temporary pipeline marking for processor error workarounds, the computer system having a processor configured to perform a method. The method includes monitoring a pipeline of the processor for an event that is predetermined to place the processor in a stuck state that results in an errant instruction execution result due to the stuck state or repeated resource contention causing performance degradation. The pipeline is marked for a workaround action based on detecting the event. A clearing action is triggered based on the marking of the pipeline. The marking of the pipeline is cleared based on the triggering of the clearing action.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: February 21, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Erez Barak, Steven R. Carlough, Eyal Gonen, Juergen Haess, Silvia M. Mueller
  • Publication number: 20170046739
    Abstract: Techniques for generating marketing lead intelligence information are described. Some embodiments provide a marketing activity support system (“MASS”) configured to generate lead intelligence by aggregating marketing activity information and customer information. In one embodiment, the MASS transmits a marketing message that references a Web page or other marketing content. Next, the MASS receives tracking information about activities of a customer with respect to the referenced Web page. The MASS then generates lead intelligence information about the customer by aggregating the tracking information, personal information about the customer, and/or information about an associated marketing campaign. The MASS may then present the generated lead intelligence information, such as by displaying details about the customer and their activities with respect to the Web page.
    Type: Application
    Filed: October 26, 2016
    Publication date: February 16, 2017
    Inventors: Erez Barak, Brian Scott Goffman
  • Patent number: 9552591
    Abstract: Techniques for generating marketing lead intelligence information are described. Some embodiments provide a marketing activity support system (“MASS”) configured to generate lead intelligence by aggregating marketing activity information and customer information. In one embodiment, the MASS transmits a marketing message that references a Web page or other marketing content. Next, the MASS receives tracking information about activities of a customer with respect to the referenced Web page. The MASS then generates lead intelligence information about the customer by aggregating the tracking information, personal information about the customer, and/or information about an associated marketing campaign. The MASS may then present the generated lead intelligence information, such as by displaying details about the customer and their activities with respect to the Web page.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: January 24, 2017
    Assignee: Marketo, Inc.
    Inventors: Erez Barak, Brian Scott Goffman
  • Publication number: 20160357638
    Abstract: Embodiments include a computer system for temporary pipeline marking for processor error workarounds, the computer system having a processor configured to perform a method. The method includes monitoring a pipeline of the processor for an event that is predetermined to place the processor in a stuck state that results in an errant instruction execution result due to the stuck state or repeated resource contention causing performance degradation. The pipeline is marked for a workaround action based on detecting the event. A clearing action is triggered based on the marking of the pipeline. The marking of the pipeline is cleared based on the triggering of the clearing action.
    Type: Application
    Filed: August 30, 2016
    Publication date: December 8, 2016
    Inventors: Erez Barak, Steven R. Carlough, Eyal Gonen, Juergen Haess, Silvia M. Mueller