Patents by Inventor Erez Izenberg

Erez Izenberg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10790862
    Abstract: Systems and methods in accordance with various embodiments of the present disclosure provide approaches for mapping entries to a cache using a function, such as cyclic redundancy check (CRC). The function can calculate a colored cache index based on a main memory address. The function may cause consecutive address cache indexes to be spread throughout the cache according to the indexes calculated by the function. In some embodiments, each data context may be associated with a different function, enabling different types of packets to be processed while sharing the same cache, reducing evictions of other data contexts and improving performance. Various embodiments can identify a type of packet as the packet is received, and lookup a mapping function based on the type of packet. The function can then be used to lookup the corresponding data context for the packet from the cache, for processing the packet.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: September 29, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Ofer Frishman, Erez Izenberg, Guy Nakibly
  • Patent number: 10747700
    Abstract: Techniques disclosed herein relate to dynamically configurable multi-stage pipeline processing units. In one embodiment, a circuit includes a plurality of processing engines and a plurality of switches. Each of the plurality of processing engines includes an input port and an output port. Each of the plurality of switches comprises two input ports and two output ports. For each processing engine, the input port of the processing engine is electrically coupled to one of the switches, the output port of the processing engine is electrically coupled to another one of the switches, and the input port of the processing engine is electrically coupled to the output port of each of the processing engines by the switches.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: August 18, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Adiel Sarusi, Ron Diamant, Ori Weber, Erez Izenberg
  • Publication number: 20200257454
    Abstract: Methods and apparatus are disclosed for securely erasing partitions of reconfigurable logic devices such as FPGAs in a multi-tenant server environment. In one example, a method of securely erasing an FPGA includes identifying one partition of previously-programmed resources in the FPGA, erasing the identified partition by storing new values in memory or storage elements of the identified partition, and storing new values in memory or storage elements of additional external resources electrically connected to the integrated circuit and associated with the identified partition. Thus, other partitions and subsequent users of the identified partition are prevented from accessing the securely erased data. A configuration circuit, accessible by a host computer via DMA, can be programmed into the FPGA reconfigurable logic for performing the disclosed erasing operations.
    Type: Application
    Filed: April 30, 2020
    Publication date: August 13, 2020
    Applicant: Amazon Technologies, Inc.
    Inventors: Mark Bradley Davis, Erez Izenberg, Robert Michael Johnson, Asif Khan, Islam Mohamed Hatem Abdulfattah Mohamed Atta, Nafea Bshara, Christopher Joseph Pettey
  • Patent number: 10742555
    Abstract: A method and corresponding apparatus for detecting network congestion. The method includes capturing, using a local clock of a sender device, a send time of an outgoing packet sent from the sender device to a receiver device through a forward route, and capturing, using the local clock of the sender device, a receive time of an acknowledgment packet sent from the receiver device to the sender device through a backward route. The acknowledgment packet contains timing information, generated using a local clock of the receiver device, for determining an internal latency of the receiver device. A round trip time is computed as a difference between the send time and the receive time. The internal latency is subtracted from the round trip time to compute a total propagation time. If the total propagation time is above a threshold, the forward route and the backward route are changed.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: August 11, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Leah Shalev, Ron Diamant, Erez Izenberg, Nafea Bshara
  • Patent number: 10742779
    Abstract: An integrated circuit device may include a configurable packet parser that is programmable to simultaneously process multiple protocols to separate packet headers from payload data of network packets. The separated packet headers and payload data can be stored in respective memories. Replacement packet headers can be generated by a programmable header builder from the separated packet headers according to configurable commands, and new packets can be generated from the replacement packet headers and the payload data.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: August 11, 2020
    Assignee: Amazon Technologies, Inc.
    Inventor: Erez Izenberg
  • Patent number: 10727966
    Abstract: In various implementations, provided are techniques for distributing network time across a network using multiple grand masters (e.g., master time keepers). These techniques include having multiple grand masters simultaneously providing time to the network. Simultaneous means that all the grand masters are active at the same time, and none are designated as backups. In various implementations, the nodes in the network can simultaneously synchronize to network times provided by more than grand masters so that the nodes can obtain more than one network time. Using these multiple network times, nodes configured as clients can determine one network time. The client devices can then use the single network time in applications that require a time.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: July 28, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Erez Izenberg, Nafea Bshara
  • Patent number: 10705995
    Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a plurality of reconfigurable logic regions. Each reconfigurable region can include hardware that is configurable to implement an application logic design. The host logic can be used for separately encapsulating each of the reconfigurable logic regions. The host logic can include a plurality of data path functions where each data path function can include a layer for formatting data transfers between a host interface and the application logic of a corresponding reconfigurable logic region. The host interface can be configured to apportion bandwidth of the data transfers generated by the application logic of the respective reconfigurable logic regions.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: July 7, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Asif Khan, Islam Mohamed Hatem Abdulfattah Mohamed Atta, Robert Michael Johnson, Mark Bradley Davis, Christopher Joseph Pettey, Nafea Bshara, Erez Izenberg
  • Patent number: 10708241
    Abstract: A hardware security accelerator includes a configurable parser that is configured to receive a packet and to extract from the packet headers associated with a set of protocols. The security accelerator also includes a packet type detection unit to determine a type of the packet in response to the set of protocols and to generate a packet type identifier indicative of the type of the packet. A configurable security unit includes a configuration unit and a configurable security engine. The configuration unit configures the configurable security engine according to the type of the packet and to content of at least one of the headers extracted from the packet. The configurable security engine performs security processing of the packet to provide at least one security result.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: July 7, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Ron Diamant, Nafea Bshara, Leah Shalev, Erez Izenberg
  • Publication number: 20200151137
    Abstract: Apparatus and methods are disclosed herein for remote, direct memory access (RDMA) technology that enables direct memory access from one host computer memory to another host computer memory over a physical or virtual computer network according to a number of different RDMA protocols. In one example, a method includes receiving remote direct memory access (RDMA) packets via a network adapter, deriving a protocol index identifying an RDMA protocol used to encode data for an RDMA transaction associated with the RDMA packets, applying the protocol index to a generate RDMA commands from header information in at least one of the received RDMA packets, and performing an RDMA operation using the RDMA commands.
    Type: Application
    Filed: December 3, 2019
    Publication date: May 14, 2020
    Applicant: Amazon Technologies, Inc.
    Inventors: Erez Izenberg, Leah Shalev, Nafea Bshara, Guy Nakibly, Georgy Machulsky
  • Patent number: 10642492
    Abstract: Methods and apparatus are disclosed for securely erasing partitions of reconfigurable logic devices such as FPGAs in a multi-tenant server environment. In one example, a method of securely erasing an FPGA includes identifying one partition of previously-programmed resources in the FPGA, erasing the identified partition by storing new values in memory or storage elements of the identified partition, and storing new values in memory or storage elements of additional external resources electrically connected to the integrated circuit and associated with the identified partition. Thus, other partitions and subsequent users of the identified partition are prevented from accessing the securely erased data. A configuration circuit, accessible by a host computer via DMA, can be programmed into the FPGA reconfigurable logic for performing the disclosed erasing operations.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: May 5, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Mark Bradley Davis, Erez Izenberg, Robert Michael Johnson, Asif Khan, Islam Mohamed Hatem Abdulfattah Mohamed Atta, Nafea Bshara, Christopher Joseph Pettey
  • Patent number: 10621134
    Abstract: Provided are systems and methods for generating transactions with a configurable port. In some implementations, a peripheral device is provided. The peripheral device comprises a configurable port. In some implementations, the configurable port may be configured to receive a first transaction. In these implementations, the first transactions may include an address. The address may include a transaction attribute. In some implementations, the configurable port may extract the transaction attribute and a transaction address from the address. The configurable port may further generate a second transaction that includes the transaction attribute and the transaction address. The configurable port may also transmit the second transaction.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: April 14, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Adi Habusha, Nafea Bshara, Itay Poleg, Erez Izenberg, Guy Nakibly, Matthew Shawn Wilson
  • Patent number: 10616116
    Abstract: Disclosed herein are techniques for classifying input network packets evenly into a plurality of classes. An apparatus includes an input port configured to receive a plurality of network packets. The apparatus also includes processing logic configured to receive the plurality of network packets from the input port and classify each packet of the plurality of network packets. For each packet, whether a condition is met is determined, a most recently used hash operation is selected when the condition is not met or a new hash operation is selected when the condition is met; and the selected hash operation is performed on the packet using at least a portion of the packet as an input value to classify the packet. The most recently used hash operation and the new hash operation are configured to classify packets having the same input value into different classes.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: April 7, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Nafea Bshara, Erez Izenberg, Said Bshara, Brian William Barrett
  • Patent number: 10614006
    Abstract: An interrupt request generating process can include determining a first interrupt triggering event has occurred after a predetermined period of time in which no interrupt triggering event occurred. In response to determining that the first interrupt triggering event has occurred, the interrupt request generating process may generate a first interrupt request without adding an intentional delay, and initiating a timer configured to expire after a predetermined time interval. When a second interrupt triggering event is determined to have occurred before the timer expires, a second interrupt request is delayed from being generated until the timer expires.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: April 7, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Said Bshara, Erez Izenberg, Yaniv Shapira, Nafea Bshara
  • Patent number: 10594476
    Abstract: A hardware cipher module to cipher a packet. The cipher module includes a key scheduling engine and a ciphering engine. The key scheduling engine is configured to receive a compact key and iteratively generate a set of round keys, including a first round key, based on the compact key and determine, based upon a cipher mode indication and a type of ciphering whether to generate a key-scheduling-done indication after the first round key is generated and before all of the set of round keys are generated or to generate the key-scheduling-done indication after all of the set of round keys is generated. The ciphering engine is configured to begin to cipher the packet with one of the set of round keys as a result of receiving the key schedule done indication.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: March 17, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Ron Diamant, Nafea Bshara, Erez Izenberg
  • Publication number: 20200057747
    Abstract: A technique for remote direct memory access (RDMA) may include receiving a packet that was sent over a network, and determining the packet has metadata indicative of acceleration. The technique may also include selecting a queue having minimal storage stages to process the packet, and writing the data of the packet to an application memory using the datapath associated with the queue. Amended metadata can be generated to indicate that the data has been written to the application memory, and the amended metadata can be stored in a software accessible buffer.
    Type: Application
    Filed: October 23, 2019
    Publication date: February 20, 2020
    Inventors: Erez Izenberg, Leah Shalev, Georgy Machulsky, Nafea Bshara
  • Patent number: 10509764
    Abstract: Apparatus and methods are disclosed herein for remote, direct memory access (RDMA) technology that enables direct memory access from one host computer memory to another host computer memory over a physical or virtual computer network according to a number of different RDMA protocols. In one example, a method includes receiving remote direct memory access (RDMA) packets via a network adapter, deriving a protocol index identifying an RDMA protocol used to encode data for an RDMA transaction associated with the RDMA packets, applying the protocol index to a generate RDMA commands from header information in at least one of the received RDMA packets, and performing an RDMA operation using the RDMA commands.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: December 17, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Erez Izenberg, Leah Shalev, Nafea Bshara, Guy Nakibly, Georgy Machulsky
  • Publication number: 20190364136
    Abstract: A system, comprising: a configurable parser that comprises one or more configurable parsing engines, wherein the configurable parser is arranged to receive a packet and to extract from the packet headers associated with a set of protocols that comprises at least one protocol; a packet type detection unit that is arranged to determine a type of the packet in response to the set of protocols; and a configurable data integrity unit that comprises a configuration unit and at least one configurable data integrity engine; wherein the configuration unit is arranged to configure the at least one configurable data integrity engine according to the set of protocols; and wherein the at least one configurable data integrity engine is arranged to perform data integrity processing of the packet to provide at least one data integrity result
    Type: Application
    Filed: June 7, 2019
    Publication date: November 28, 2019
    Inventors: Ofer Naaman, Erez Izenberg, Nafea Bshara
  • Patent number: 10459875
    Abstract: According to an embodiment of the invention there may be provided a method for hybrid remote direct memory access (RDMA), the method may include: (i) receiving, by a first computer, a packet that was sent over a network from a second computer; wherein the packet may include data and metadata; (ii) determining, in response to the metadata, whether the data should be (a) directly written to a first application memory of the first computer by a first hardware accelerator of the first computer; or (b) indirectly written to the first application memory; (iii) indirectly writing the data to the first application memory if it determined that the data should be indirectly written to the first application memory; (iv) if it determined that the data should be directly written to the first application memory then: (iv.a) directly writing, by the first hardware accelerator the data to the first application memory without writing the data to any buffer of the operating system; and (iv.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: October 29, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Erez Izenberg, Leah Shalev, Georgy Machulsky, Nafea Bshara
  • Publication number: 20190258597
    Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.
    Type: Application
    Filed: February 27, 2019
    Publication date: August 22, 2019
    Inventors: Islam Atta, Christopher Joseph Pettey, Asif Khan, Robert Michael Johnson, Mark Bradley Davis, Erez Izenberg, Nafea Bshara, Kypros Constantinides
  • Publication number: 20190215021
    Abstract: Systems and methods in accordance with various embodiments of the present disclosure provide approaches for mapping entries to a cache using a function, such as cyclic redundancy check (CRC). The function can calculate a colored cache index based on a main memory address. The function may cause consecutive address cache indexes to be spread throughout the cache according to the indexes calculated by the function. In some embodiments, each data context may be associated with a different function, enabling different types of packets to be processed while sharing the same cache, reducing evictions of other data contexts and improving performance. Various embodiments can identify a type of packet as the packet is received, and lookup a mapping function based on the type of packet. The function can then be used to lookup the corresponding data context for the packet from the cache, for processing the packet.
    Type: Application
    Filed: January 7, 2019
    Publication date: July 11, 2019
    Inventors: Ofer Frishman, Erez Izenberg, Guy Nakibly