Patents by Inventor Erez Kohavi

Erez Kohavi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for efficient pre-silicon debug
    Patent number: 9734263
    Abstract: Described is a method and apparatus for efficient pre-silicon validation of an integrated circuit. The method comprises: analyzing an architectural verification environment associated with a hardware description language (HDL) architecture of an integrated circuit, recognizing method calls associated with the architectural verification environment, and generating a list of recognized method calls that is loaded for a debug program to debug the HDL architecture of the integrated circuit.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: August 15, 2017
    Assignee: Intel Corporation
    Inventors: Erez Kohavi, Evgeniy Ainbinder
  • METHOD, APPARATUS, AND SYSTEM FOR EFFICIENT PRE-SILICON DEBUG
    Publication number: 20140181767
    Abstract: Described are method, apparatus, and system for efficient pre-silicon validation of an integrated circuit. The method comprises: analyzing architectural verification environment associated with a hardware description language (HDL) architecture of an integrated circuit; recognizing method calls associated with the architectural verification environment; and generating a list of recognized method calls, the list for being loaded for a debug program to debug the HDL architecture of the integrated circuit.
    Type: Application
    Filed: December 20, 2012
    Publication date: June 26, 2014
    Inventors: Erez Kohavi, Evgeniy Ainbinder