Patents by Inventor Erez Reches
Erez Reches has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10205586Abstract: A network device includes a packet processor, a plurality of interface circuits, a phase-locked loop (PLL) circuit and a configuration controller. The interface circuits are configured to transmit and receive signals to/from other devices that are coupled to the network device. A master interface circuit among the interface circuits is configured to recover a network clock from a received signal. The PLL circuit is configured to generate an interface clock based on a system clock of the network device and a configuration of the PLL circuit and to provide the interface clock to the plurality of interface circuits to govern communication timings of the interface circuits. The configuration controller is configured to detect a difference of the interface clock relative to the recovered network clock, and to determine the configuration of the PLL circuit based on the difference to govern operation of the PLL circuit.Type: GrantFiled: February 2, 2017Date of Patent: February 12, 2019Assignee: MARVELL WORLD TRADE LTD.Inventors: Gideon Paul, Erez Reches, Zvi Leib Shmilovici
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Publication number: 20170222792Abstract: A network device includes a packet processor, a plurality of interface circuits, a phase-locked loop (PLL) circuit and a configuration controller. The interface circuits are configured to transmit and receive signals to/from other devices that are coupled to the network device. A master interface circuit among the interface circuits is configured to recover a network clock from a received signal. The PLL circuit is configured to generate an interface clock based on a system clock of the network device and a configuration of the PLL circuit and to provide the interface clock to the plurality of interface circuits to govern communication timings of the interface circuits. The configuration controller is configured to detect a difference of the interface clock relative to the recovered network clock, and to determine the configuration of the PLL circuit based on the difference to govern operation of the PLL circuit.Type: ApplicationFiled: February 2, 2017Publication date: August 3, 2017Applicant: MARVELL WORLD TRADE LTDInventors: Gideon Paul, Erez Reches, Zvi Leib Shmilovici
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Patent number: 8972755Abstract: An integrated circuit includes an operational circuit module receiving a supply voltage from a voltage regulator external to the integrated circuit, and an adaptive voltage scaling module to adjust the supply voltage based on performance characteristics of the operational circuit module. The adaptive voltage scaling module can include a performance monitoring module disposed on the integrated circuit and configured to generate at least an indicator corresponding to at least one performance characteristic of the operational circuit module. The adaptive scaling module can include a voltage requirement determination and voltage feedback generator module disposed on the integrated circuit and coupled to the performance monitoring module. The voltage requirement determination and voltage feedback generator module is configured to output a feedback voltage signal having a voltage level as a function of at least the indicator.Type: GrantFiled: December 19, 2013Date of Patent: March 3, 2015Assignee: Marvell Israel (M.I.S.L) Ltd.Inventors: Meir Hasko, Erez Reches, Reuven Ecker, Ido Bourstein
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Patent number: 8615669Abstract: An integrated circuit includes an operational circuit module receiving a supply voltage from a voltage regulator external to the integrated circuit, and an adaptive voltage scaling module to adjust the supply voltage based on performance characteristics of the operational circuit module. The adaptive voltage scaling module can include a performance monitoring module disposed on the integrated circuit and configured to generate at least an indicator corresponding to at least one performance characteristic of the operational circuit module. The adaptive scaling module can include a voltage requirement determination and voltage feedback generator module disposed on the integrated circuit and coupled to the performance monitoring module. The voltage requirement determination and voltage feedback generator module is configured to output a feedback voltage signal having a voltage level as a function of at least the indicator.Type: GrantFiled: September 13, 2012Date of Patent: December 24, 2013Assignee: Marvell Israel (M.I.S.L) Ltd.Inventors: Meir Hasko, Erez Reches, Reuven Ecker, Ido Bourstein
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Patent number: 8370654Abstract: Aspects of the disclosure provide an integrated circuit. The integrated circuit includes a first operational circuit module receiving a first supply voltage from a first voltage regulator that is external to the integrated circuit, and a first adaptive voltage scaling module to adjust the first supply voltage based on performance characteristics of the first operational circuit module. In an embodiment of the disclosure, the first adaptive voltage scaling module includes a first performance monitoring module. The performance monitoring module is disposed on the integrated circuit, and is configured to generate at least a first indicator corresponding to at least one performance characteristic of the first operational circuit module. Further, the first adaptive scaling module includes a first voltage requirement determination and voltage feedback generator module that is disposed on the integrated circuit, and is coupled to the first performance monitoring module.Type: GrantFiled: March 24, 2010Date of Patent: February 5, 2013Assignee: Marvell Israel (M.I.S.L) Ltd.Inventors: Meir Hasko, Erez Reches, Reuven Ecker, Ido Bourstein
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Patent number: 7849370Abstract: To facilitate measurement of the jitter tolerance of circuitry such as serializer/deserializer (SERDES) circuitry, test circuitry is provided that can add jitter to a data signal. The jitter added is preferably controllable and variable with respect to such parameters as jitter frequency (i.e., how rapid is the jitter) and/or amplitude (i.e., how large or great is the amount of the jitter).Type: GrantFiled: October 4, 2006Date of Patent: December 7, 2010Assignee: Marvell Israel (M.I.S.L.) Ltd.Inventors: David Moshe, Erez Reches, Ido Naishtein
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Patent number: 7664146Abstract: An alignment circuit comprises a plurality of inputs that receive corresponding data signals, wherein each of the corresponding data signals includes a training pattern. A plurality of delay lines correspond to each of the plurality of inputs, receive the corresponding data signals, receive a plurality of corresponding delay signals, and delay each of the data signals according to the corresponding delay signals. A controller receives the corresponding data signals and generates the plurality of corresponding delay signals based on the training patterns of respective ones of the data signals.Type: GrantFiled: January 29, 2007Date of Patent: February 16, 2010Assignee: Marvell Israel (M.I.S.L.) Ltd.Inventor: Erez Reches
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Patent number: 7439785Abstract: To facilitate measurement of the jitter tolerance of circuitry such as serializer/deserializer (SERDES) circuitry, test circuitry is provided that can add jitter to a data signal. The jitter added is preferably controllable and variable with respect to such parameters as jitter frequency (i.e., how rapid is the jitter) and/or amplitude (i.e., how large or great is the amount of the jitter).Type: GrantFiled: October 4, 2006Date of Patent: October 21, 2008Assignee: Marvell Israel (M.I.S.L.) Ltd.Inventors: David Moshe, Erez Reches, Ido Naishtein
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Publication number: 20070036209Abstract: To facilitate measurement of the jitter tolerance of circuitry such as serializer/deserializer (SERDES) circuitry, test circuitry is provided that can add jitter to a data signal. The jitter added is preferably controllable and variable with respect to such parameters as jitter frequency (i.e., how rapid is the jitter) and/or amplitude (i.e., how large or great is the amount of the jitter).Type: ApplicationFiled: October 4, 2006Publication date: February 15, 2007Applicant: Marvell Semiconductor Israel Ltd.Inventors: David Moshe, Erez Reches, Ido Naishtein
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Publication number: 20070024336Abstract: To facilitate measurement of the jitter tolerance of circuitry such as serializer/deserializer (SERDES) circuitry, test circuitry is provided that can add jitter to a data signal. The jitter added is preferably controllable and variable with respect to such parameters as jitter frequency (i.e., how rapid is the jitter) and/or amplitude (i.e., how large or great is the amount of the jitter).Type: ApplicationFiled: October 4, 2006Publication date: February 1, 2007Applicant: Marvell Semiconductor Israel Ltd.Inventors: David Moshe, Erez Reches, Ido Naishtein
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Patent number: 7170907Abstract: A method, apparatus, and computer-readable media for aligning n data signals received over a parallel bus, each of the n data signals comprising a training pattern, wherein n is at least two, comprises delaying each of the n data signals in accordance with a corresponding analog delay signal, thereby providing n corresponding delayed data signals; providing each of the corresponding analog delay signals based on the training pattern in the respective delayed data signal; delaying each of the delayed data signals by m bit times in accordance with a corresponding digital delay signal, thereby providing n corresponding aligned data signals, wherein m is greater than, or equal to, zero; and providing each of the corresponding digital delay signals based on the training pattern in the corresponding delayed data signal.Type: GrantFiled: September 18, 2002Date of Patent: January 30, 2007Assignee: Marvell Semiconductor Israel Ltd.Inventor: Erez Reches
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Publication number: 20060255848Abstract: To facilitate measurement of the jitter tolerance of circuitry such as serializer/deserializer (SERDES) circuitry, test circuitry is provided that can add jitter to a data signal. The jitter added is preferably controllable and variable with respect to such parameters as jitter frequency (i.e., how rapid is the jitter) and/or amplitude (i.e., how large or great is the amount of the jitter).Type: ApplicationFiled: July 21, 2006Publication date: November 16, 2006Applicant: Marvell Semiconductor Israel Ltd.Inventors: David Moshe, Erez Reches, Ido Naishtein
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Patent number: 7135904Abstract: To facilitate measurement of the jitter tolerance of circuitry such as serializer/deserializer (SERDES) circuitry, test circuitry is provided that can add jitter to a data signal. The jitter added is preferably controllable and variable with respect to such parameters as jitter frequency (i.e., how rapid is the jitter) and/or amplitude (i.e., how large or great is the amount of the jitter).Type: GrantFiled: May 13, 2004Date of Patent: November 14, 2006Assignee: Marvell Semiconductor Israel Ltd.Inventors: David Moshe, Erez Reches, Ido Naishtein