Abstract: A semiconductor device includes a storage element write unit including a storage element configured to be electrically written only once and store two values, a write controller connected to the storage element through a first node signal and configured to perform a write to the storage element based on a write control signal instructing a write to the storage element, and a write state detection circuit configured to detect that the storage element is in a write state based on a measurement signal obtained by measuring the first node signal. In a case where the write controller receives a detection signal indicating that the storage element is in the write state from the write state detection circuit after start of a write to the storage element, the write controller stops write operation after a lapse of a predetermined time from detection of the write state of the storage element.

Abstract: Some demonstrative embodiments include a Metal-Oxide-Semiconductor (MOS) transistor including a split-gate structure. For example, an Integrated Circuit (IC) may include a MOS including a body; a source; a drain; and a split-gate structure including a control gate and at least one voltage-controlled Field-Plate (FP), the control gate is between the source and the voltage-controlled FP, the voltage-controlled FP is between the control gate and the drain, the control gate configured to switch the MOS transistor between an on state and an off state according to a switching voltage; and a voltage controller configured to apply a variable control voltage to the voltage-controlled FP, the variable control voltage based on at least one control parameter, the at least one control parameter including at least one of a load current driven by the MOS transistor or a switching frequency of the switching voltage.

Abstract: Some demonstrative embodiments include a Metal-Oxide-Semiconductor (MOS) transistor including a split-gate structure. For example, an Integrated Circuit (IC) may include a MOS including a body; a source; a drain; and a split-gate structure including a control gate and at least one voltage-controlled Field-Plate (FP), the control gate is between the source and the voltage-controlled FP, the voltage-controlled FP is between the control gate and the drain, the control gate configured to switch the MOS transistor between an on state and an off state according to a switching voltage; and a voltage controller configured to apply a variable control voltage to the voltage-controlled FP, the variable control voltage based on at least one control parameter, the at least one control parameter including at least one of a load current driven by the MOS transistor or a switching frequency of the switching voltage.

Abstract: An operational transconductance amplifier, that may include a first differential pair that comprises a first transistor and a second transistor that are coupled to each other at a certain node; wherein the first differential pair is configured to convert a differential input voltage to first and second output currents; a current source that is coupled to the certain node and may include an adjustable current sources; and a feedback unit that is coupled to the certain node and is configured to (a) receive the differential input voltage, and maintain a voltage of the certain node substantially fixed regardless of changes in the differential input voltage.

Abstract: An operational transconductance amplifier, that may include a first differential pair that comprises a first transistor and a second transistor that are coupled to each other at a certain node; wherein the first differential pair is configured to convert a differential input voltage to first and second output currents; a current source that is coupled to the certain node and may include an adjustable current sources; and a feedback unit that is coupled to the certain node and is configured to (a) receive the differential input voltage, and maintain a voltage of the certain node substantially fixed regardless of changes in the differential input voltage.

Abstract: A device for overcurrent protection, the device may include a main transistor that is configured to supply, via an output node, a load current to a load; a current limiting resistor; a replica transistor that is configured to provide a replica current to the current limiting resistor; wherein the replica current is smaller than the load current, wherein a value of the replica current is responsive to a value of the load current; an amplifier; a current limiting transistor; a variable signal source that is configured to output a reference signal; wherein a value of the reference signal is based on a main transistor voltage; wherein the amplifier is configured to prevent the load current from exceeding a first load current threshold by biasing the main transistor and the replica transistor with a bias signal; wherein a value of the bias signal is responsive to the reference signal and to the replica current.

Abstract: A device for overcurrent protection, the device may include a main transistor that is configured to supply, via an output node, a load current to a load; a current limiting resistor; a replica transistor that is configured to provide a replica current to the current limiting resistor; wherein the replica current is smaller than the load current, wherein a value of the replica current is responsive to a value of the load current; an amplifier; a current limiting transistor; a variable signal source that is configured to output a reference signal; wherein a value of the reference signal is based on a main transistor voltage; wherein the amplifier is configured to prevent the load current from exceeding a first load current threshold by biasing the main transistor and the replica transistor with a bias signal; wherein a value of the bias signal is responsive to the reference signal and to the replica current.

Abstract: A soft-start circuit for a switching regulator (e.g., a buck converter) in which the soft-start circuit supplies a DC ramp voltage to the switch regulator's pre-driver such that the pulsed gate voltage supplied to power switch during the initial soft-start operating phase includes a series of pulses having amplitudes that respectively gradually change (e.g., sequentially increase from 0V to the system operating voltage), whereby the regulated output voltage passed from the power switch to the load is gradually increased at a rate that prevents voltage overshoot and inrush current. The DC ramp voltage is generated, for example, by a current source that begins charging a capacitor at the beginning of the initial soft-start operating phase. This arrangement allows a constant-frequency ramp signal generated by a single oscillator to be shared by multiple switch regulators that are fabricated on an IC chip.

Abstract: An endoscope system includes a host device and an endoscope including a very small area CMOS image sensor having only four pads (power, ground, digital in, analog out), and including an array of 4T pixels and associated control circuitry for performing correlated double sampling (CDS) to generate analog reset level and analog signal level values associated with light detected by photodiodes in each pixel. Instead of processing the analog values on-chip, the analog reset values and analog signal values are transmitted in separate sets one row at a time along with interleaved synchronization signals by way of a single analog contact pad to the host device of the endoscopic system, which uses the synchronization signals to reconstruct the sensor's internal clock in order to process the analog values. The endoscope housing thus requires only four wires and is made very small.

Abstract: A soft-start circuit for a switching regulator (e.g., a buck converter) in which the soft-start circuit supplies a DC ramp voltage to the switch regulator's pre-driver such that the pulsed gate voltage supplied to power switch during the initial soft-start operating phase includes a series of pulses having amplitudes that respectively gradually change (e.g., sequentially increase from 0V to the system operating voltage), whereby the regulated output voltage passed from the power switch to the load is gradually increased at a rate that prevents voltage overshoot and inrush current. The DC ramp voltage is generated, for example, by a current source that begins charging a capacitor at the beginning of the initial soft-start operating phase. This arrangement allows a constant-frequency ramp signal generated by a single oscillator to be shared by multiple switch regulators that are fabricated on an IC chip.

Abstract: A modified bootstrap circuit utilized, for example, in a high voltage DC/DC CMOS buck converter to convert a high input voltage (e.g., 24V) to a regulated voltage (e.g., 4V) for use, for example, by an LED driver circuit. The bootstrap circuit utilizes a feedback diode and a PMOS switch to avoid high reverse diode voltages across a low voltage bootstrap diode. A bootstrapped buck converter implements the bootstrap circuit to generate a high gate voltage on a high-side NMOS switch during all operating phases. The PMOS switch is controlled by the NMOS switch's output voltage to pass a system voltage (e.g., 5V) through the bootstrap diode whenever the output voltage drops low (e.g., 0V), and to shut off when the output voltage subsequently rises such that the feedback diode forward biases to pass the output voltage to the anode of the bootstrap diode.

Abstract: A very small area CMOS image sensor, e.g., for an endoscopic system, includes only four pads (power, ground, digital in, analog out), and includes an array of 4T pixels and associated control circuitry for performing correlated double sampling (CDS) to generate analog reset level and analog signal level values associated with light detected by photodiodes in each pixel. Instead of processing the analog values on-chip, the analog reset values and analog signal values are transmitted in separate sets one row at a time along with interleaved synchronization signals by way of a single analog contact pad, e.g., to a host device of an endoscopic system, which uses the synchronization signals to reconstruct the sensor's internal clock in order to process the analog values. An endoscope housing incorporating the CMOS image sensor thus requires only four wires.

Abstract: A modified bootstrap circuit utilized, for example, in a high voltage DC/DC CMOS buck converter to convert a high input voltage (e.g., 24V) to a regulated voltage (e.g., 4V) for use, for example, by an LED driver circuit. The bootstrap circuit utilizes a feedback diode and a PMOS switch to avoid high reverse diode voltages across a low voltage bootstrap diode. A bootstrapped buck converter implements the bootstrap circuit to generate a high gate voltage on a high-side NMOS switch during all operating phases. The PMOS switch is controlled by the NMOS switch's output voltage to pass a system voltage (e.g., 5V) through the bootstrap diode whenever the output voltage drops low (e.g., 0V), and to shut off when the output voltage subsequently rises such that the feedback diode forward biases to pass the output voltage to the anode of the bootstrap diode.

Abstract: A very small area CMOS image sensor, e.g., for an endoscopic system, includes only four pads (power, ground, digital in, analog out), and includes an array of 4T pixels and associated control circuitry for performing correlated double sampling (CDS) to generate analog reset level and analog signal level values associated with light detected by photodiodes in each pixel. Instead of processing the analog values on-chip, the analog reset values and analog signal values are transmitted in separate sets one row at a time along with interleaved synchronization signals by way of a single analog contact pad, e.g., to a host device of an endoscopic system, which uses the synchronization signals to reconstruct the sensor's internal clock in order to process the analog values. An endoscope housing incorporating the CMOS image sensor thus requires only four wires.

Abstract: A large image sensor structure is created by tiling a plurality of image sensor dies, wherein each of the image sensor dies includes a pixel array that extends to three edges of the die, and control circuitry located along a fourth edge of the die. None of the control circuitry required to access the pixel array (e.g., none of the row driver circuitry) is located in the pixel array, thereby enabling consistent spacing of pixels across the pixel array. Because the pixel array of each image sensor die extends to three edges of the die, the pixel array of each image sensor die can abut up to three pixel arrays in other image sensor dies to form a large image sensor structure having 2×N tiled image sensor dies.

Abstract: A single-poly electrically erasable/programmable CMOS logic memory cell for mobile applications includes a CMOS inverter that share a single polysilicon floating gate, and an enhanced control capacitor including a control gate capacitor and an optional isolated P-well (IPW) capacitor formed below the control gate capacitor. The control gate capacitor includes a polysilicon control gate that is interdigitated with the floating gate and serves as a capacitor plate to induce Fowler-Nordheim (F-N) injection or Band-to-Band Tunneling (BBT) to both program and erase the floating gate. The IPW capacitor is provided in the otherwise unused space below the control gate capacitor by a IPW that is separated from the control/floating gates by a dielectric layer and is electrically connected to the control gate. Both F-N injection and BBT program/erase are performed at 5V or less.

Abstract: A current control circuit is coupled in parallel with the current paths of a differential comparator circuit to ensure that a substantially constant current is drawn from a current source during all operating phases of a comparator. The current control circuit is biased by a reference voltage, which is also used to bias a V? input terminal of the differential comparator circuit. The reference voltage is stored by a sample capacitor, which is charged by applying the reference voltage to a V+ input terminal of the differential comparator circuit while coupling an output terminal of the differential comparator circuit to the sample capacitor in a unity feedback configuration.

Abstract: A large image sensor structure is created by tiling a plurality of image sensor dies, wherein each of the image sensor dies includes a pixel array that extends to three edges of the die, and control circuitry located along a fourth edge of the die. None of the control circuitry required to access the pixel array (e.g., none of the row driver circuitry) is located in the pixel array, thereby enabling consistent spacing of pixels across the pixel array. Because the pixel array of each image sensor die extends to three edges of the die, the pixel array of each image sensor die can abut up to three pixel arrays in other image sensor dies to form a large image sensor structure having 2×N tiled image sensor dies.

Abstract: An imaging system including column-parallel ADCs that operate in response to a single slope global ramp signal and a matched global ramp line signal that has a voltage representative of a dark pixel value. The signal paths of the global ramp signal and the matched global ramp line signal are matched to minimize noise effects. Prior to performing a pixel read operation, the global ramp signal is increased through a first voltage range (below the dark pixel value) to ensure that the column-parallel ADCs are operating in a linear range. The first voltage range can be adjusted to cancel offset error associated with the column parallel ADCs. The column-parallel ADCs provide output signals having a full voltage swing between VDD and ground.

Abstract: A current control circuit is coupled in parallel with the current paths of a differential comparator circuit to ensure that a substantially constant current is drawn from a current source during all operating phases of a comparator. The current control circuit is biased by a reference voltage, which is also used to bias a V? input terminal of the differential comparator circuit. The reference voltage is stored by a sample capacitor, which is charged by applying the reference voltage to a V+ input terminal of the differential comparator circuit while coupling an output terminal of the differential comparator circuit to the sample capacitor in a unity feedback configuration.