Patents by Inventor Erez Shaizaf
Erez Shaizaf has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11936570Abstract: A modular switch and a method that includes (a) first tier switching elements that comprise input output (IO) ports; and (b) second tier switching elements that are coupled to the first tier switching elements in a non-blocking manner. The first tier switching elements are configured to perform traffic management of traffic, and perform substantially all egress processing and ingress processing of the traffic; wherein the traffic management comprises load balancing, traffic shaping and flow-based reordering. The second tier switching elements are configured to (a) provide a shared memory space to the first tier switching elements, (b) perform substantially all of the queuing of traffic and (c) send, to the first tier switching elements, status information related to the status of shared memory resources. The first tier switching elements are configured to perform the traffic management based, at least in part, on the status information.Type: GrantFiled: September 22, 2019Date of Patent: March 19, 2024Assignee: XSIGHT LABS LTD.Inventors: Guy Koren, Gal Malach, Erez Shaizaf
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Patent number: 11677673Abstract: A system for managing traffic between servers, the system may include first tier switches that are coupled to the servers; second tier switches that are coupled to the first tier switches and to third tier switches; and controllers. Wherein each first tier switch comprises first queues. Wherein each second tier switch comprises second queues. The controllers are configured to control a traffic between the first tier switches and the second tier switches attributed to the traffic between the servers, (a) on, at least, a queue granularity; (b) while controlling some first queues to provide buffer extension to some second queues, and (c) while controlling some second queues to provide buffer extension to some first queues.Type: GrantFiled: September 6, 2021Date of Patent: June 13, 2023Assignee: XSIGHT LABS LTD.Inventors: Guy Koren, Gal Malach, Erez Shaizaf
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Patent number: 11552884Abstract: A method for managing traffic in a computerized system that may include routers and at least one edge device, the method may include performing traffic management operations for controlling traffic related to the routers while executing a first traffic management operations by the at least one edge device, and executing second traffic management operations by the routers.Type: GrantFiled: September 22, 2020Date of Patent: January 10, 2023Assignee: XSIGHT LABS LTD.Inventors: Guy Koren, Gal Malach, Erez Shaizaf
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Patent number: 11251245Abstract: A method for responding to a failure of a main die of a switch data-plane device, the method may include applying a secondary packet forwarding process by multiple chiplets, following the failure of the main die and during at least a part of an execution of a synchronous graceful process that follows the failure of the main die; wherein the multiple chiplets are interconnected to each other by a secondary interconnect; wherein the multiple chiplets and are coupled to the main die by a primary interconnect; wherein the applying of the secondary packet forwarding process is less complex than a primary forwarding process applied by the main die while the main die is functional.Type: GrantFiled: January 21, 2020Date of Patent: February 15, 2022Assignee: XSIGHT LABS LTD.Inventors: Carmi Arad, Guy Koren, Gal Malach, Erez Shaizaf
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Patent number: 11115341Abstract: A system for managing traffic between servers, the system may include first tier switches that are coupled to the servers; second tier switches that are coupled to the first tier switches and to third tier switches; and controllers. Wherein each first tier switch comprises first queues. Wherein each second tier switch comprises second queues. The controllers are configured to control a traffic between the first tier switches and the second tier switches attributed to the traffic between the servers, (a) on, at least, a queue granularity; (b) while controlling some first queues to provide buffer extension to some second queues, and (c) while controlling some second queues to provide buffer extension to some first queues.Type: GrantFiled: September 22, 2019Date of Patent: September 7, 2021Assignee: XSIGHT LABS LTD.Inventors: Guy Koren, Gal Malach, Erez Shaizaf
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Patent number: 8924795Abstract: A distributed debug system including processing elements connected to perform a plurality of processing functions on a received data unit, a debug trap unit, a debug trace dump logic unit, and a debug initiator unit is provided. At least two of the processing elements include a debug trap unit that has a first debug enable input and output, and a first debug thread. The first debug thread holds at least a first debug trap circuit having a match signal output connected to the first debug enable output. The first debug trap circuit filters a part of the data unit, compares a filtering result with a debug value, and provides a match signal to the match signal output. The debug trace dump logic unit dumps debug trace data to a buffer associated with the data unit on reception of a match event.Type: GrantFiled: September 30, 2009Date of Patent: December 30, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Gil Moran, Evgeni Ginzburg, Adi Katz, Erez Shaizaf
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Publication number: 20120185730Abstract: A distributed debug system including processing elements connected to perform a plurality of processing functions on a received data unit, a debug trap unit, a debug trace dump logic unit, and a debug initiator unit is provided. At least two of the processing elements include a debug trap unit that has a first debug enable input and output, and a first debug thread. The first debug thread holds at least a first debug trap circuit having a match signal output connected to the first debug enable output. The first debug trap circuit filters a part of the data unit, compares a filtering result with a debug value, and provides a match signal to the match signal output. The debug trace dump logic unit dumps debug trace data to a buffer associated with the data unit on reception of a match event.Type: ApplicationFiled: September 30, 2009Publication date: July 19, 2012Applicant: Freescale Semiconductor, Imc.Inventors: Gil Moran, Evgeni Ginzburg, Adi Katz, Erez Shaizaf
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Patent number: 7761760Abstract: A method for designing an integrated circuit, the method includes: providing an initial definition of a boundary scan register that includes identical super-cells adapted to be connected to multiple pin types; and determining the configuration of each super-cell by providing at least one pin type indication signal to each super-cell. An integrated circuit that includes a boundary scan super-cell, the boundary scan super-cell includes first circuitry adapted to be connected to at least one type of integrated circuit pin; characterized by further including a second circuitry, connected to first circuitry, wherein the second circuitry is adapted to receive at least one pin type indication signal and in response allows the boundary scan super-cell to be connected to at least one additional type of an integrated circuit pin.Type: GrantFiled: May 4, 2005Date of Patent: July 20, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Erez Shaizaf, Kostya Korchomkin, Tal Mazor
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Publication number: 20080204076Abstract: A method for designing an integrated circuit, the method includes: providing an initial definition of a boundary scan register that includes identical super-cells adapted to be connected to multiple pin types; and determining the configuration of each super-cell by providing at least one pin type indication signal to each super-cell. An integrated circuit that includes a boundary scan super-cell, the boundary scan super-cell includes first circuitry adapted to be connected to at least one type of integrated circuit pin; characterized by further including a second circuitry, connected to first circuitry, wherein the second circuitry is adapted to receive at least one pin type indication signal and in response allows the boundary scan super-cell to be connected to at least one additional type of an integrated circuit pin.Type: ApplicationFiled: May 4, 2005Publication date: August 28, 2008Applicant: Freescale Semiconductor, Inc.Inventors: Erez Shaizaf, Kostya Korchomkin, Tal Mazor