Abstract: Systems and methods are disclosed for contextual driver monitoring. In one implementation, one or more first inputs are received. The one or more first inputs are processed to identify a first object in relation to a vehicle. One or more second inputs are received. The one or more second inputs are processed to determine, based on one or more previously determined states of attentiveness associated with the driver of the vehicle in relation to one or more objects associated with the first object, a state of attentiveness of a driver of the vehicle with respect to the first object. One or more actions are initiated based on the state of attentiveness of a driver.

Abstract: Systems, devices, methods, and non-transitory computer-readable media are provided for gesture recognition and control. For example, a processor of a gesture recognition system may be configured to receive first image(s) from an image sensor and process the image(s) to detect a first position of an object. The processor may also define a first navigation region in relation to the position and define a second navigation region in relation to the first navigation region, the second region surrounding the first region. The processor may also receive second image(s) from the image sensor and process the image(s) to detect a transition of the object from the first region to the second region. The processor may also determine a first command associated with a device and that corresponds to the transition of the object from the first region to the second region and provide the determined command to the device.

Abstract: Systems, devices, methods, and non-transitory computer-readable media are provided for gesture recognition and control. For example, a processor of a gesture recognition system may be configured to receive first image(s) from an image sensor and process the image(s) to detect a first position of an object. The processor may also define a first navigation region in relation to the position and define a second navigation region in relation to the first navigation region, the second region surrounding the first region. The processor may also receive second image(s) from the image sensor and process the image(s) to detect a transition of the object from the first region to the second region. The processor may also determine a first command associated with a device and that corresponds to the transition of the object from the first region to the second region and provide the determined command to the device.

Abstract: Systems, devices, methods, and non-transitory computer-readable media are provided for gesture recognition and control. For example, a processor of a gesture recognition system may be configured to receive first image(s) from an image sensor and process the image(s) to detect a first position of an object. The processor may also define a first navigation region in relation to the position and define a second navigation region in relation to the first navigation region, the second region surrounding the first region. The processor may also receive second image(s) from the image sensor and process the image(s) to detect a transition of the object from the first region to the second region. The processor may also determine a first command associated with a device and that corresponds to the transition of the object from the first region to the second region and provide the determined command to the device.

Abstract: Video processing system, computer program product and method for managing an exchange of information between a memory unit and a decoder, the method includes: (a) retrieving, from the memory unit, a first non-zero data structure that comprises only non-zero first transform coefficient groups; wherein first transform coefficient groups are associated with a first quality level; (b) retrieving, from the memory unit, second layer information; (c) processing, by the video decoder, the second layer information and the first non-zero data structure to provide second transform coefficient groups; (c) generating, by the video decoder, a second non-zero data structure that comprises only non-zero second transform coefficient groups; wherein the second non-zero data structure is associated with a second quality level that is higher than the first quality level; (d) generating second non-zero indicators that are indicative of non-zero transform coefficient groups, wherein the second non-zero data structure is associated

Abstract: A method of encoding a video frame is disclosed in which video slices of the video frame are initially encoded in parallel using both interframe encoding and intraframe encoding. Then, after a first predetermined minimum amount of the video frame has been encoded, the method includes periodically determining whether the amount of intraframe encoded information for the frame achieves a first threshold, and when the first threshold is achieved, encoding the remainder of the video frame using only intraframe encoding. The method may include determining whether a lower second threshold is achieved based on relative complexity of the frame and quantization. The method may include performing similar comparisons on a slice by slice basis in which any one or more of the processing devices skips motion estimation and interframe encoding for corresponding video slices. A video encoder is disclosed which includes multiple processing devices and a shared memory.

Abstract: Embodiments are disclosed for a system and method for parallel processing of video signals. A multi-core processor is used to establish a master-slave relationship between a first processing core and a plurality of individual processing cores. Shared memory is used to store data and control messages. A plurality of individual private memories are associated with each of the individual processing cores; and control logic is used to establish a master-slave protocol for using the plurality of individual cores to process video data. The master processing core is operable to balance the video data processing load among the individual slave processing cores.

Abstract: A method for bit rate control within a scalable video coding system is described. The method comprises, for an access unit within a scalable encoded video bit stream, determining a bit budget for at least one spatial dependence layer within the scalable encoded video bit stream, and calculating at least one quantization parameter value for encoding the at least one spatial dependence layer based at least partly on the determined bit budget for the at least one spatial dependence layer.

Abstract: The invention pertains to a video processing system for video processing, the video processing system being arranged to assign tasks to least two parallel processing units capable of parallel processing of tasks. The video processing system is further arranged to control at least one storage device to store input video data to be processed, processed video data and a task list of video processing tasks. The video processing system is arranged to provide and/or process video data having a hierarchical enhancement structure comprising at least one basic layer and one or more enhancement layers dependent on the basic layer and/or at least one of the other enhancement layers. It is further arranged to assign at least one task of the task list to one of the parallel processing units; and to update, after the parallel processing unit has processed a task, the task list with information regarding tasks related to at least one enhancement layer dependent on the processed task.

Abstract: A method for generating cache user initiated pre-fetch requests, the method comprises initiating a sequence of user initiated pre-fetch requests; the method being characterized by: determining the timing of user initiated pre-fetch requests of the sequence of user initiated pre-fetch requests in response to: the timing of an occurrence of a last triggering event, a user initiated pre-fetch sequence delay period and a user initiated pre-fetch sequence rate.

Abstract: A method for executing an instruction, the method includes: executing a compare and configure mask instruction, wherein the executing comprises: performing a comparison to provide a comparison result; and configuring, in response to the comparison result, a multiple bit mask that is stored in a multiple-purpose register; wherein all bits of the multiple bit mask are configured to have the same value; and applying an algorithmic operation on the multiple bit mask to provide an algorithmic operation result; wherein the algorithmic operation result represents an outcome of a high level programming language conditional statement.

Abstract: A method for address comparison, the method includes: (i) receiving an input address; (ii) determining whether the input address is within a memory segment out of a group of memory segments by comparing, in parallel, the input address to memory segment boundaries of each memory segment of the group; (iii) wherein a comparison between the input address and a memory segment boundary comprises: (a) applying a XOR operation on bits of a most significant portion of the input address and corresponding bits of a most significant portion of the memory segment boundary; (b) ignoring bits of a least significant portion of the input address and corresponding bits of a least significant portion of the memory segment boundary; and (c) comparing, by utilizing a set of full comparators, between bits of an intermediate portion of the input address and corresponding bits of an intermediate portion of the memory segment boundary; wherein a location of bits that form the intermediate portion of the input address and of the memo

Abstract: Video processing system, computer program product and method for managing an exchange of information between a memory unit and a decoder, the method includes: (a) retrieving, from the memory unit, a first non-zero data structure that comprises only non-zero first transform coefficient groups; wherein first transform coefficient groups are associated with a first quality level; (b) retrieving, from the memory unit, second layer information; (c) processing, by the video decoder, the second layer information and the first non-zero data structure to provide second transform coefficient groups; (c) generating, by the video decoder, a second non-zero data structure that comprises only non-zero second transform coefficient groups; wherein the second non-zero data structure is associated with a second quality level that is higher than the first quality level; (d) generating second non-zero indicators that are indicative of non-zero transform coefficient groups, wherein the second non-zero data structure is associated

Abstract: Video processing system, computer program product and method for decoding an encoded video stream, the method includes: receiving an encoded video stream that comprises a plurality of encoded video frames, each encoded video frame comprises multiple encoded frame portions; and repeating, for each encoded frame portion: providing, to an entropy decoder, different quality level representations of the encoded frame portion and context information generated during an entropy decoding process of different quality level representations of another encoded frame portion; entropy decoding, by the entropy decoder, the different quality level representations of the frame portion based on the context information; wherein the entropy decoding comprises updating the context information; wherein the entropy decoding is selected from a group consisting of context based adaptive binary arithmetic coding (CABAC) and context based variable length coding (CBVLC); and storing the context information.

Abstract: A method of encoding a video frame is disclosed in which video slices of the video frame are initially encoded in parallel using both interframe encoding and intraframe encoding. Then, after a first predetermined minimum amount of the video frame has been encoded, the method includes periodically determining whether the amount of intraframe encoded information for the frame achieves a first threshold, and when the first threshold is achieved, encoding the remainder of the video frame using only intraframe encoding. The method may include determining whether a lower second threshold is achieved based on relative complexity of the frame and quantization. The method may include performing similar comparisons on a slice by slice basis in which any one or more of the processing devices skips motion estimation and interframe encoding for corresponding video slices. A video encoder is disclosed which includes multiple processing devices and a shared memory.

Abstract: A method for generating cache user initiated pre-fetch requests, the method comprises initiating a sequence of user initiated pre-fetch requests; the method being characterized by: determining the timing of user initiated pre-fetch requests of the sequence of user initiated pre-fetch requests in response to: the timing of an occurrence of a last triggering event, a user initiated pre-fetch sequence delay period and a user initiated pre-fetch sequence rate.

Abstract: A method for address comparison, the method includes: (i) receiving an input address; (ii) determining whether the input address is within a memory segment out of a group of memory segments by comparing, in parallel, the input address to memory segment boundaries of each memory segment of the group; (iii) wherein a comparison between the input address and a memory segment boundary comprises: (a) applying a XOR operation on bits of a most significant portion of the input address and corresponding bits of a most significant portion of the memory segment boundary; (b) ignoring bits of a least significant portion of the input address and corresponding bits of a least significant portion of the memory segment boundary; and (c) comparing, by utilizing a set of full comparators, between bits of an intermediate portion of the input address and corresponding bits of an intermediate portion of the memory segment boundary; wherein a location of bits that form the intermediate portion of the input address and of the memo

Abstract: A method for executing an instruction, the method includes: executing a compare and configure mask instruction, wherein the executing comprises: performing a comparison to provide a comparison result; and configuring, in response to the comparison result, a multiple bit mask that is stored in a multiple-purpose register; wherein all bits of the multiple bit mask are configured to have the same value; and applying an algorithmic operation on the multiple bit mask to provide an algorithmic operation result; wherein the algorithmic operation result represents an outcome of a high level programming language conditional statement.

Abstract: Embodiments are disclosed for a system and method for parallel processing of video signals. A multi-core processor is used to establish a master-slave relationship between a first processing core and a plurality of individual processing cores. Shared memory is used to store data and control messages. A plurality of individual private memories are associated with each of the individual processing cores; and control logic is used to establish a master-slave protocol for using the plurality of individual cores to process video data. The master processing core is operable to balance the video data processing load among the individual slave processing cores.

Abstract: A reconfigurable office partition system that includes movable rigid panels each comprised of a core panel mounted within a perimeter frame. Said core panel comprised of a matrix of compressed straw or other cellulose-based natural fiber lined by paper or paperboard suitable for accepting a variety of surface treatments, and also suitable for accepting nails, screws or other means for hanging or otherwise attaching articles thereon. Frames comprised of vertical and horizontal rails specially adapted to engage said core panels and further adapted to releasably and slidably attach to a series of specialty connectors.