Abstract: One illustrative IC product disclosed herein includes a first conductive line positioned at a first level within the IC product and a first conductive structure positioned at a second level within the IC product, wherein the second level is lower than the first level. In this illustrative example, the IC product also includes a second conductive structure that is conductively coupled to the first conductive line, wherein at least a portion of the second conductive structure is positioned at a level that is above the first level and wherein nearest surfaces of the first conductive structure and the second conductive structure are laterally offset from one another by a lateral distance and insulating material positioned between the nearest surfaces of the first conductive structure and the second conductive structure.

Abstract: The present disclosure relates to a method which includes generating a device layout of an eBeam based overlay (EBO OVL) structure with a minimum design rule, simulating a worst case process margin for the generated device layout of the EBO OVL structure, enabling a plurality of devices for the simulated worst case process margin for the generated device layout of the EBO OVL structure, and breaking a plurality of design rules for the enabled plurality of devices of the EBO OVL structure to generate an OVL measurement layout of the EBO OVL structure.

Abstract: The present disclosure relates to a method which includes generating a device layout of an eBeam based overlay (EBO OVL) structure with a minimum design rule, simulating a worst case process margin for the generated device layout of the EBO OVL structure, enabling a plurality of devices for the simulated worst case process margin for the generated device layout of the EBO OVL structure, and breaking a plurality of design rules for the enabled plurality of devices of the EBO OVL structure to generate an OVL measurement layout of the EBO OVL structure.

Abstract: A self-aligned quadruple patterning (SAQP) process for forming semiconductor devices utilizes a look-up table based on lithography and etch profiles to improve the critical dimension(s) of semiconductor structures such as semiconductor fins. The look-up table may include lithography and etch data, including critical dimension (CD) and sidewall angle (SWA) data for intermediate as well as final structures formed during fabrication, and may be used to improve fin CD and fin pitch in device architectures that include densely-arrayed, semi-densely arrayed and nested structures.

Abstract: A method to address overlay accuracy compensation using finFET cut isolation revisions is disclosed. For an integrated circuit (IC) layout including at least a portion of an active region including a plurality of gates extending over a plurality of fins, prior to optical proximity correction of the IC layout: the method determines a number of fins to be cut with same source/drain connection by a fin cut isolation opening, and determines a fin cut isolation pitch in the gate length direction of the plurality of gates. The method revises a size of a fin cut isolation opening in the IC layout based on a number of fins to be cut with same source/drain connection by the fin cut isolation opening and the fin cut isolation pitch in the gate length direction. The revision in size of the fin cut isolation compensates for overlay inaccuracy.

Abstract: A self-aligned quadruple patterning (SAQP) process for forming semiconductor devices utilizes a look-up table based on lithography and etch profiles to improve the critical dimension(s) of semiconductor structures such as semiconductor fins. The look-up table may include lithography and etch data, including critical dimension (CD) and sidewall angle (SWA) data for intermediate as well as final structures formed during fabrication, and may be used to improve fin CD and fin pitch in device architectures that include densely-arrayed, semi-densely arrayed and nested structures.

Abstract: A method to address overlay accuracy compensation using finFET cut isolation revisions is disclosed. For an integrated circuit (IC) layout including at least a portion of an active region including a plurality of gates extending over a plurality of fins, prior to optical proximity correction of the IC layout: the method determines a number of fins to be cut with same source/drain connection by a fin cut isolation opening, and determines a fin cut isolation pitch in the gate length direction of the plurality of gates. The method revises a size of a fin cut isolation opening in the IC layout based on a number of fins to be cut with same source/drain connection by the fin cut isolation opening and the fin cut isolation pitch in the gate length direction. The revision in size of the fin cut isolation compensates for overlay inaccuracy.