Patents by Inventor Erh-Kun Lai

Erh-Kun Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8110429
    Abstract: A resistance random access memory in a bridge structure is disclosed that comprises a contact structure where first and second electrodes are located within the contact structure. The first electrode has a circumferential extending shape, such as an annular shape, surrounding an inner wall of the contact structure. The second electrode is located within an interior of the circumferential extending shape and separated from the first electrode by an insulating material. A resistance memory bridge is in contact with an edge surface of the first and second electrodes. The first electrode in the contact structure is connected to a transistor and the second electrode in the contact structure is connected to a bit line. A bit line is connected to the second electrode by a self-aligning process.
    Type: Grant
    Filed: October 2, 2009
    Date of Patent: February 7, 2012
    Assignee: Macronix International Co., Ltd.
    Inventors: ChiaHua Ho, Erh-Kun Lai, Kuang Yeu Hsieh
  • Patent number: 8111541
    Abstract: A method and structure of a bistable resistance random access memory comprise a plurality of programmable resistance random access memory cells where each programmable resistance random access memory cell includes multiple memory members for performing multiple bits for each memory cell. The bistable RRAM includes a first resistance random access member connected to a second resistance random access member through interconnect metal liners and metal oxide strips. The first resistance random access member has a first resistance value Ra, which is determined from the thickness of the first resistance random access member based on the deposition of the first resistance random access member. The second resistance random access member has a second resistance value Rb, which is determined from the thickness of the second resistance random access member based on the deposition of the second resistance random access member.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: February 7, 2012
    Assignee: Macronix International Co., Ltd.
    Inventors: Erh-Kun Lai, ChiaHua Ho, Kuang Yeu Hsieh
  • Patent number: 8106376
    Abstract: A memory device including a programmable resistive memory material is described along with methods for manufacturing the memory device. A memory device disclosed herein includes top and bottom electrodes and a multilayer stack disposed between the top and bottom electrodes. The multilayer stack includes a memory element comprising programmable resistive memory material and has a sidewall surface. An air gap is adjacent to the sidewall surface and self-aligned to the memory element.
    Type: Grant
    Filed: October 23, 2007
    Date of Patent: January 31, 2012
    Assignee: Macronix International Co., Ltd.
    Inventors: Erh Kun Lai, Kuang Yeu Hsieh, ChiaHua Ho
  • Publication number: 20120018845
    Abstract: Memory devices and methods for manufacturing are described herein. A memory device described herein includes a plurality of memory cells. Memory cells in the plurality of memory cells comprise respective bipolar junction transistors and memory elements. The bipolar junction transistors are arranged in a common collector configuration and include an emitter comprising doped polysilicon having a first conductivity type, the emitter contacting a corresponding word line in a plurality of word lines to define a pn junction. The bipolar junction transistors include a portion of the corresponding word line underlying the emitter acting as a base, and a collector comprising a portion of the single-crystalline substrate underlying the base.
    Type: Application
    Filed: October 3, 2011
    Publication date: January 26, 2012
    Applicants: International Business Machines Corporation, Macronix International Co., Ltd.
    Inventors: Hsiang-Lan Lung, Erh-Kun Lai, Bipin Rajendran, Chung H. Lam
  • Patent number: 8101483
    Abstract: A semiconductor device includes an insulating layer, a channel structure, an insulating structure and a gate. The channel structure includes a channel bridge for connecting two platforms. The bottom of the channel bridge is separated from the insulating layer by a distance, and the channel bridge has a plurality of separated doping regions. The insulating structure wraps around the channel bridge, and the gate wraps around the insulating structure.
    Type: Grant
    Filed: July 22, 2010
    Date of Patent: January 24, 2012
    Assignee: Macronix International Co., Ltd.
    Inventors: Erh-Kun Lai, Hang-Ting Lue
  • Patent number: 8093661
    Abstract: A silicide element separates a single crystal silicon node from an underlying silicon substrate, and is capable of acting as a conductive element for interconnecting devices on the device. The single crystal silicon node can act as one terminal of a diode, and a second semiconductor node on top of it can act as the other terminal of the diode. The single crystal silicon node can act as one of the terminals of the transistor, and second and third semiconductor nodes are formed in series on top of it, providing a vertical transistor structure, which can be configured as a field effect transistor or bipolar junction transistor. The silicide element can be formed by a process that consumes a base of a protruding single crystal element by silicide formation processes, while shielding upper portions of the protruding element from the silicide formation process.
    Type: Grant
    Filed: January 7, 2009
    Date of Patent: January 10, 2012
    Assignee: Macronix International Co., Ltd.
    Inventors: Hsiang-Lan Lung, Erh-Kun Lai
  • Patent number: 8089137
    Abstract: A memory device includes a diode driver and a data storage element, such as an element comprising phase change memory material, and in which the diode driver comprises a silicide element on a silicon substrate with a single crystal silicon node on the silicide element. The silicide element separates the single crystal silicon node from the underlying silicon substrate, preventing the flow of carriers from the single crystal silicon node into the substrate, and is capable of acting as a conductive element for interconnecting devices on the device. The single crystal silicon node acts as one terminal of a diode, and a second semiconductor node is formed on top of it, acting as the other terminal of the diode.
    Type: Grant
    Filed: January 7, 2009
    Date of Patent: January 3, 2012
    Assignee: Macronix International Co., Ltd.
    Inventors: Hsiang-Lan Lung, Erh-Kun Lai
  • Patent number: 8080440
    Abstract: A phase change random access memory PCRAM device is described suitable for use in large-scale integrated circuits. An exemplary memory device has a pipe-shaped first electrode formed from a first electrode layer on a sidewall of a sidewall support structure. A sidewall spacer insulating member is formed from a first oxide layer and a second, “L-shaped,” electrode is formed on the insulating member. An electrical contact is connected to the horizontal portion of the second electrode. A bridge of memory material extends from a top surface of the first electrode to a top surface of the second electrode across a top surface of the sidewall spacer insulating member.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: December 20, 2011
    Assignee: Macronix International Co., Ltd.
    Inventors: Erh-Kun Lai, ChiaHua Ho, Kuang Yeu Hsieh
  • Publication number: 20110305074
    Abstract: A memory device is described that comprises a plurality of bit lines and an array of vertical transistors arranged on the plurality of bit lines. A plurality of word lines is formed along rows of vertical transistors in the array which comprise thin film sidewalls of word line material and arranged so that the thin film sidewalls merge in the row direction, and do not merge in the column direction, to form word lines. The word lines provide “surrounding gate” structures for embodiments in which the vertical transistors are field effect transistors. Memory elements are formed in electrical communication with the vertical transistors. A fully self-aligned process is provided in which the word lines and memory elements are aligned with the vertical transistors without additional patterning steps.
    Type: Application
    Filed: June 15, 2010
    Publication date: December 15, 2011
    Applicants: International Business Machines Corporation, Macronix International Co., Ltd.
    Inventors: Hsiang-Lan Lung, Chung Hon Lam, Erh-Kun Lai, Matthew J. Breitwisch
  • Patent number: 8072793
    Abstract: Memory devices are described along with methods for manufacturing. A memory device as described herein includes a plurality of memory cells located between word lines and bit lines. Each memory cell comprises a diode and a plurality of memory elements each comprising one or more metal-oxygen compounds, the diode and the plurality of memory elements arranged in electrical series along a current path between a corresponding word line and a corresponding bit line.
    Type: Grant
    Filed: September 4, 2008
    Date of Patent: December 6, 2011
    Assignee: Macronix International Co., Ltd.
    Inventors: Ming-Daou Lee, Erh-Kun Lai, Kuang Yeu Hsieh
  • Patent number: 8067815
    Abstract: Memory devices are described along with methods for manufacturing. A memory device as described herein includes a first electrode and a second electrode. The memory device further includes a diode and an anti-fuse metal-oxide memory element comprising aluminum oxide and copper oxide. The diode and the metal-oxide memory element are arranged in electrical series between the first electrode and the second electrode.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: November 29, 2011
    Assignee: Macronix International Co., Lt.d.
    Inventors: Wei-Chih Chien, Kuo-Pin Chang, Yi-Chou Chen, Erh-Kun Lai, Kuang-Yeu Hsieh
  • Patent number: 8067762
    Abstract: A bistable resistance random access memory is described for enhancing the data retention in a resistance random access memory member. A dielectric member, e.g. the bottom dielectric member, underlies the resistance random access memory member which improves the SET/RESET window in the retention of information. The deposition of the bottom dielectric member is carried out by a plasma-enhanced chemical vapor deposition or by high-density-plasma chemical vapor deposition. One suitable material for constructing the bottom dielectric member is a silicon oxide. The bistable resistance random access memory includes a bottom dielectric member disposed between a resistance random access member and a bottom electrode or bottom contact plug. Additional layers including a bit line, a top contact plug, and a top electrode disposed over the top surface of the resistance random access memory member. Sides of the top electrode and the resistance random access memory member are substantially aligned with each other.
    Type: Grant
    Filed: November 16, 2006
    Date of Patent: November 29, 2011
    Assignee: Macronix International Co., Ltd.
    Inventors: ChiaHua Ho, Erh-Kun Lai, Kuang Yeu Hsieh
  • Publication number: 20110286283
    Abstract: A 3D memory device is described which includes bottom and top memory cubes having respective arrays of vertical NAND string structures. A common source plane comprising a layer of conductive material is between the top and bottom memory cubes. The source plane is supplied a bias voltage such as ground, and is selectively coupled to an end of the vertical NAND string structures of the bottom and top memory cubes. Memory cells in a particular memory cube are read using current through the particular vertical NAND string between the source plane and a corresponding bit line coupled to another end of the particular vertical NAND string.
    Type: Application
    Filed: May 21, 2010
    Publication date: November 24, 2011
    Applicant: Macronix International Co., Ltd.
    Inventors: HSIANG-LAN LUNG, Hang-Ting Lue, Yen-Hao Shih, Erh-Kun Lai, Ming Hsiu Lee, Tien-Yen Wang
  • Patent number: 8039392
    Abstract: A memory device has a sidewall insulating member with a sidewall insulating member length according to a first spacer layer thickness. A first electrode formed from a second spacer layer having a first electrode length according to a thickness of a second spacer layer and a second electrode formed from the second spacer layer having a second electrode length according to the thickness of the second spacer layer are formed on sidewalls of the sidewall insulating member. A bridge of memory material having a bridge width extends from a top surface of the first electrode to a top surface of the second electrode across a top surface of the sidewall insulating member, wherein the bridge comprises memory material.
    Type: Grant
    Filed: September 23, 2010
    Date of Patent: October 18, 2011
    Assignee: Macronix International Co., Ltd.
    Inventors: Erh-Kun Lai, ChiaHua Ho, Kuang Yeu Hsieh
  • Publication number: 20110250729
    Abstract: A method for fabricating a memory is described. Word lines are provided in a first direction. Bit lines are provided in a second direction. A top electrode is formed connecting to a corresponding word line. A bottom electrode is formed connecting to a corresponding bit line. A resistive layer is formed on the bottom electrode. At least two separate L-shaped liners are formed, wherein each L-shaped liner has variable resistive materials on both ends of the L-shaped liner and each L-shaped liner is coupled between the top electrode and the resistive layer.
    Type: Application
    Filed: June 20, 2011
    Publication date: October 13, 2011
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Erh-Kun Lai, Chia-Hua Ho, Kuang-Yeu Hsieh
  • Publication number: 20110241100
    Abstract: A stacked non-volatile memory device comprises a plurality of bit line and word line layers stacked on top of each other. The bit line layers comprise a plurality of bit lines that can be formed using advanced processing techniques making fabrication of the device efficient and cost effective. The device can be configured for NAND operation.
    Type: Application
    Filed: June 16, 2011
    Publication date: October 6, 2011
    Applicant: Macronix International Co., Ltd.
    Inventors: ERH-KUN LAI, Hang-Ting Lue, Kuang-Yeu Hsieh
  • Patent number: 8030635
    Abstract: Memory devices and methods for manufacturing are described herein. A memory device described herein includes a plurality of memory cells. Memory cells in the plurality of memory cells comprise respective bipolar junction transistors and memory elements. The bipolar junction transistors are arranged in a common collector configuration and include an emitter comprising doped polysilicon having a first conductivity type, the emitter contacting a corresponding word line in a plurality of word lines to define a pn junction. The bipolar junction transistors include a portion of the corresponding word line underlying the emitter acting as a base, and a collector comprising a portion of the single-crystalline substrate underlying the base.
    Type: Grant
    Filed: January 13, 2009
    Date of Patent: October 4, 2011
    Assignees: Macronix International Co., Ltd., International Business Machines Corporation
    Inventors: Hsiang-Lan Lung, Erh-Kun Lai, Bipin Rajendran, Chung Hon Lam
  • Patent number: 8026136
    Abstract: Memory cells comprising: a semiconductor substrate having at least two source/drain regions separated by a channel region; a charge-trapping structure disposed above the channel region; and a gate disposed above the charge-trapping structure; wherein the charge-trapping structure comprises a bottom insulating layer, a first charge-trapping layer, and a second charge-trapping layer, wherein an interface between the bottom insulating layer and the substrate has a hydrogen concentration of less than about 3×1011/cm?2, and methods for forming such memory cells.
    Type: Grant
    Filed: December 26, 2007
    Date of Patent: September 27, 2011
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Yen-Hao Shih, Min-Ta Wu, Shih-Chin Lee, Jung-Yu Hsieh, Erh-Kun Lai, Kuang Yeu Hsieh
  • Patent number: 8022466
    Abstract: Memory cells including a semiconductor layer having at least two source/drain regions disposed below a surface of the semiconductor layer and separated by a channel region; a lower insulating layer disposed above the channel region; a charge storage layer disposed above the lower insulating layer; an upper insulating multi-layer structure disposed above the charge storage layer, wherein the upper insulating multi-layer structure comprises a polysilicon material layer interposed between a first dielectric layer and a second dielectric layer; and a gate disposed above the upper insulating multi-layer structure are described along with arrays thereof and methods of operation.
    Type: Grant
    Filed: October 27, 2006
    Date of Patent: September 20, 2011
    Assignee: Macronix International Co., Ltd.
    Inventors: Erh-Kun Lai, Yen-Hao Shih, Tzu-Hsuan Hsu, Shih-Chih Lee, Jung-Yu Hsieh, Kuang-Yeu Hsieh
  • Patent number: 8022489
    Abstract: An air tunnel floating gate memory cell includes an air tunnel defined over a substrate. A first polysilicon layer (floating gate) is defined over the air tunnel. An oxide layer is disposed over the first polysilicon layer such that the oxide layer caps the first polysilicon layer and defines the sidewalls of the air tunnel. A second polysilicon layer, functioning as a word line, is defined over the oxide layer. A method for making an air tunnel floating gate memory cell is also disclosed. A sacrificial layer is formed over a substrate. A first polysilicon layer is formed over the sacrificial layer. An oxide layer is deposited over the first polysilicon layer such that the oxide layer caps the first polysilicon layer and defines the sidewalls of the sacrificial layer. A hot phosphoric acid (H3PO4) dip is used to etch away the sacrificial layer to form an air tunnel.
    Type: Grant
    Filed: May 20, 2005
    Date of Patent: September 20, 2011
    Assignee: Macronix International Co., Ltd.
    Inventors: Hang-Ting Lue, Erh-Kun Lai, Kuang Yeu Hsieh