Patents by Inventor ERHU ZHENG
ERHU ZHENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230223452Abstract: A semiconductor structure and a forming method thereof are provided. The method includes: providing a substrate, a dummy spacer being formed on a side wall of the gate structure, a contact etch stop layer being formed on a side wall of the dummy spacer, and a source/drain doped area being formed in the substrate on two sides of the gate structure; forming a sacrificial dielectric layer above tops of the source/drain doped area and the gate structure; forming a source/drain plug running through the sacrificial dielectric layer; etching the sacrificial dielectric layer until a top of the dummy spacer is exposed; removing, after the top of the dummy spacer is exposed, the dummy spacer to form a gap between the contact etch stop layer and the side wall of the gate structure; and forming a top dielectric layer filling between the source/drain plugs.Type: ApplicationFiled: March 21, 2023Publication date: July 13, 2023Applicants: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Bo Su, Hansu OH, Chunsheng ZHENG, Erhu ZHENG, Haiyang ZHANG
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Patent number: 11393685Abstract: The present disclosure provides a method for forming a semiconductor structure. The method includes providing a to-be-etched layer; forming a plurality of initial sidewall spacers on the to-be-etched layer; and performing at least one modification treatment process on the plurality of initial sidewall spacers to form a plurality of sidewall spacers. Each of the at least one modification treatment process includes modifying the plurality of initial sidewall spacers to form a transition layer on the top and sidewall surfaces of each initial sidewall spacer of the plurality of initial sidewall spacers, and then removing the transition layer.Type: GrantFiled: September 23, 2020Date of Patent: July 19, 2022Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Bo Su, Shiliang Ji, Erhu Zheng, Yan Wang, Haiyang Zhang
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Publication number: 20210134595Abstract: The present disclosure provides a method for forming a semiconductor structure. The method includes providing a to-be-etched layer; forming a plurality of initial sidewall spacers on the to-be-etched layer; and performing at least one modification treatment process on the plurality of initial sidewall spacers to form a plurality of sidewall spacers. Each of the at least one modification treatment process includes modifying the plurality of initial sidewall spacers to form a transition layer on the top and sidewall surfaces of each initial sidewall spacer of the plurality of initial sidewall spacers, and then removing the transition layer.Type: ApplicationFiled: September 23, 2020Publication date: May 6, 2021Inventors: Bo SU, Shiliang JI, Erhu ZHENG, Yan WANG, Haiyang ZHANG
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Patent number: 10957550Abstract: A semiconductor structure and a formation method thereof are provided. The formation method includes: providing a base, the base including a pattern dense region and a pattern isolated region; forming a plurality of separate hard mask layers on the base, where adjacent hard mask layers and the base define an opening, and an opening of the pattern isolated region is wider than an opening of the pattern dense region; forming a trimming layer at least on a side wall of the opening of the pattern isolated region, the trimming layer and the hard mask layer constituting a mask structure layer; and etching, using the mask structure layer as a mask, a portion of the thickness of the base exposed by the opening to form a plurality of target pattern layers protruding from the remaining base. Embodiments and implementations of the present disclosure are advantageous for improving a critical dimension uniformity of a target pattern layer in each region.Type: GrantFiled: August 9, 2019Date of Patent: March 23, 2021Assignees: Semiconductor Manufacturing (Beijing) International Corporation, Semconductor Manufacturing (Shanghai) International CorporationInventors: Haiyang Zhang, Erhu Zheng
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Publication number: 20200279748Abstract: A semiconductor structure and a formation method thereof are provided. The formation method includes: providing a base, the base including a pattern dense region and a pattern isolated region; forming a plurality of separate hard mask layers on the base, where adjacent hard mask layers and the base define an opening, and an opening of the pattern isolated region is wider than an opening of the pattern dense region; forming a trimming layer at least on a side wall of the opening of the pattern isolated region, the trimming layer and the hard mask layer constituting a mask structure layer; and etching, using the mask structure layer as a mask, a portion of the thickness of the base exposed by the opening to form a plurality of target pattern layers protruding from the remaining base. Embodiments and implementations of the present disclosure are advantageous for improving a critical dimension uniformity of a target pattern layer in each region.Type: ApplicationFiled: August 9, 2019Publication date: September 3, 2020Applicants: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) CorporationInventors: Haiyang ZHANG, Erhu ZHENG
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Patent number: 10763169Abstract: A semiconductor device includes a substrate structure comprising an active region, a first interlayer dielectric layer on the active region, and a first opening in the first interlayer dielectric layer and extending to the active region, at least one gate structure in the first opening and comprising spacers on sidewalls of the first opening, a gate dielectric layer on the active region, a metal gate on the gate dielectric layer, and a hardmask on the metal gate and having a first recess in a middle portion of its upper surface, the gate dielectric layer, the metal gate, and the hardmask being between the spacers, a second interlayer dielectric layer on the first dielectric layer and on at least a portion of the hardmask, and a second opening adjacent to the at least one gate structure in the first opening and exposing the spacers and a surface of the active region.Type: GrantFiled: February 7, 2019Date of Patent: September 1, 2020Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventors: Chenglong Zhang, Erhu Zheng, Haiyang Zhang
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Patent number: 10593550Abstract: This application relates to the technical field of semiconductors, and teaches methods for manufacturing a semiconductor structure. One implementation of a method includes: forming a semiconductor layer at a surface of a to-be-etched material layer on a substrate; forming an amorphous carbon layer on the semiconductor layer; forming a patterned mask layer on the amorphous carbon layer; and etching the amorphous carbon layer, the semiconductor layer, and the to-be-etched material layer using the patterned mask layer as a mask. This application may improve uniformity of the amorphous carbon layer, so that a position of a pattern that is formed after the to-be-etched material layer is etched does not deviate from an expected position, and a shape of the pattern is an expected shape.Type: GrantFiled: May 10, 2018Date of Patent: March 17, 2020Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International CorporationInventors: Erhu Zheng, Jinhe Qi
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Patent number: 10453968Abstract: A semiconductor device and its manufacturing method are presented, relating to semiconductor techniques. The manufacturing method includes: forming a multi-layer structure comprising one or more semiconductor structures on a substrate. The semiconductor structure is formed by: forming a first semiconductor layer; and forming a second semiconductor layer on the first semiconductor layer, wherein in at least one semiconductor structure, an ion implantation is conducted on a portion of the first semiconductor layer to form a doped region therein; etching the multi-layer structure to form a fin structure and a support structure on at least one side of the fin structure, with the support structure comprising at least a portion of the doped region; and removing the first semiconductor layer in the fin structure so that the second semiconductor layer becomes hanging over the substrate. This inventive concept ameliorates the bending issue of the second semiconductor layer.Type: GrantFiled: May 31, 2018Date of Patent: October 22, 2019Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventors: Hai Yang Zhang, Erhu Zheng
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Publication number: 20190189511Abstract: A semiconductor device includes a substrate structure comprising an active region, a first interlayer dielectric layer on the active region, and a first opening in the first interlayer dielectric layer and extending to the active region, at least one gate structure in the first opening and comprising spacers on sidewalls of the first opening, a gate dielectric layer on the active region, a metal gate on the gate dielectric layer, and a hardmask on the metal gate and having a first recess in a middle portion of its upper surface, the gate dielectric layer, the metal gate, and the hardmask being between the spacers, a second interlayer dielectric layer on the first dielectric layer and on at least a portion of the hardmask, and a second opening adjacent to the at least one gate structure in the first opening and exposing the spacers and a surface of the active region.Type: ApplicationFiled: February 7, 2019Publication date: June 20, 2019Applicants: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Chenglong Zhang, Erhu Zheng, Haiyang Zhang
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Patent number: 10242910Abstract: A method for manufacturing a semiconductor device includes providing a substrate structure having an action region and a gate structure having a gate dielectric layer, a gate, a hardmask. The method also includes forming a first dielectric layer on the gate structure, forming a second dielectric layer on the first dielectric layer, performing a surface treatment on the second dielectric layer so that the upper surface of the second dielectric layer is flush with the upper surface of the mask member, which has a first recess is in its middle portion, forming a third dielectric layer on the second dielectric layer covering the mask member and selectively etching the third dielectric layer and the second dielectric layer relative to the first dielectric layer and the hardmask to form an opening adjacent to the gate structure and exposing the first dielectric layer on sidewalls of the gate structure.Type: GrantFiled: June 16, 2017Date of Patent: March 26, 2019Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventors: Chenglong Zhang, Erhu Zheng, Haiyang Zhang
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Publication number: 20180351001Abstract: A semiconductor device and its manufacturing method are presented, relating to semiconductor techniques. The manufacturing method includes: forming a multi-layer structure comprising one or more semiconductor structures on a substrate. The semiconductor structure is formed by: forming a first semiconductor layer; and forming a second semiconductor layer on the first semiconductor layer, wherein in at least one semiconductor structure, an ion implantation is conducted on a portion of the first semiconductor layer to form a doped region therein; etching the multi-layer structure to form a fin structure and a support structure on at least one side of the fin structure, with the support structure comprising at least a portion of the doped region; and removing the first semiconductor layer in the fin structure so that the second semiconductor layer becomes hanging over the substrate. This inventive concept ameliorates the bending issue of the second semiconductor layer.Type: ApplicationFiled: May 31, 2018Publication date: December 6, 2018Inventors: Hai Yang ZHANG, Erhu ZHENG
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Publication number: 20180342393Abstract: This application relates to the technical field of semiconductors, and teaches methods for manufacturing a semiconductor structure. One implementation of a method includes: forming a semiconductor layer at a surface of a to-be-etched material layer on a substrate; forming an amorphous carbon layer on the semiconductor layer; forming a patterned mask layer on the amorphous carbon layer; and etching the amorphous carbon layer, the semiconductor layer, and the to-be-etched material layer using the patterned mask layer as a mask. This application may improve uniformity of the amorphous carbon layer, so that a position of a pattern that is formed after the to-be-etched material layer is etched does not deviate from an expected position, and a shape of the pattern is an expected shape.Type: ApplicationFiled: May 10, 2018Publication date: November 29, 2018Applicants: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Erhu Zheng, Jinhe Qi
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Patent number: 9978760Abstract: A method for manufacturing a semiconductor device may include the following steps: providing a spacer structure on a first side of a stack structure, wherein the stack structure includes a mask and a conductor; providing an etch stop layer, wherein a portion of the etch stop layer directly contacts both the mask and a portion of the spacer structure; providing a dielectric material member on the etch stop layer; partially removing the first dielectric material member to expose the portion of the etch stop layer; removing the portion of the etch stop layer to expose the portion of the spacer structure; removing the portion of the spacer structure to expose a side of the mask and to form a first spacer; and providing a second spacer, which directly contacts both the first spacer and the side of the mask.Type: GrantFiled: October 20, 2016Date of Patent: May 22, 2018Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventors: Yiying Zhang, Erhu Zheng
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Patent number: 9911593Abstract: A method for fabricating an NAND flash memory includes providing a semiconductor substrate with a core region and a peripheral region, forming a plurality of discrete gate stack structures in the core region with neighboring gate stack structures separated by a first dielectric layer. The method further includes forming a flowable dielectric layer on the first dielectric layer and the gate stack structures, and forming a solid dielectric layer through a solidification treatment process performed on the flowable dielectric layer. Voids and seams formed in the top portion of the first dielectric layer are filled by the solid dielectric layer. The method also includes removing the solid dielectric layer and a portion of the first dielectric layer to expose a top portion of the gate stack structures, and forming a metal silicide layer on each gate stack structure.Type: GrantFiled: August 23, 2016Date of Patent: March 6, 2018Assignees: SEIMCONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventors: Erhu Zheng, Shiliang Ji, Yiying Zhang
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Publication number: 20180005886Abstract: A method for manufacturing a semiconductor device includes providing a substrate structure having an action region and a gate structure having a gate dielectric layer, a gate, a hardmask. The method also includes forming a first dielectric layer on the gate structure, forming a second dielectric layer on the first dielectric layer, performing a surface treatment on the second dielectric layer so that the upper surface of the second dielectric layer is flush with the upper surface of the mask member, which has a first recess is in its middle portion, forming a third dielectric layer on the second dielectric layer covering the mask member and selectively etching the third dielectric layer and the second dielectric layer relative to the first dielectric layer and the hardmask to form an opening adjacent to the gate structure and exposing the first dielectric layer on sidewalls of the gate structure.Type: ApplicationFiled: June 16, 2017Publication date: January 4, 2018Inventors: CHENGLONG ZHANG, ERHU ZHENG, HAIYANG ZHANG
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Publication number: 20170179142Abstract: A method for manufacturing a semiconductor device may include the following steps: providing a spacer structure on a first side of a stack structure, wherein the stack structure includes a mask and a conductor; providing an etch stop layer, wherein a portion of the etch stop layer directly contacts both the mask and a portion of the spacer structure; providing a dielectric material member on the etch stop layer; partially removing the first dielectric material member to expose the portion of the etch stop layer; removing the portion of the etch stop layer to expose the portion of the spacer structure; removing the portion of the spacer structure to expose a side of the mask and to form a first spacer; and providing a second spacer, which directly contacts both the first spacer and the side of the mask.Type: ApplicationFiled: October 20, 2016Publication date: June 22, 2017Inventors: Yiying ZHANG, Erhu ZHENG
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Publication number: 20170170011Abstract: A method for fabricating an NAND flash memory includes providing a semiconductor substrate with a core region and a peripheral region, forming a plurality of discrete gate stack structures in the core region with neighboring gate stack structures separated by a first dielectric layer. The method further includes forming a flowable dielectric layer on the first dielectric layer and the gate stack structures, and forming a solid dielectric layer through a solidification treatment process performed on the flowable dielectric layer. Voids and seams formed in the top portion of the first dielectric layer are filled by the solid dielectric layer. The method also includes removing the solid dielectric layer and a portion of the first dielectric layer to expose a top portion of the gate stack structures, and forming a metal silicide layer on each gate stack structure.Type: ApplicationFiled: August 23, 2016Publication date: June 15, 2017Inventors: ERHU ZHENG, SHILIANG JI, YIYING ZHANG