Abstract: A semiconductor device includes: an insulating circuit substrate; a semiconductor element including a first main electrode bonded to a first conductor layer of the insulating circuit substrate via a first bonding material, a semiconductor substrate deposited on the first main electrode, and a second main electrode deposited on the semiconductor substrate; and a resistive element including a bottom surface electrode bonded to a second conductor layer of the insulating circuit substrate via a second bonding material, a resistive layer with one end electrically connected to the bottom surface electrode, and a top surface electrode electrically connected to another end of the resistive layer, wherein the first main electrode includes a first bonded layer bonded to the first bonding material, the bottom surface electrode includes a second bonded layer bonded to the second bonding material, and the first bonded layer and the second bonded layer have a common structure.

Abstract: A syringe assembly includes a plate-shaped seal member that seals a distal opening of a distal nozzle portion of a syringe; and a tubular cover member. The cover member has a base portion and a mounting portion. The mounting portion has two claw portions, two first column portions arranged on both sides of one of the two claw portions, and two second column portions arranged on both sides of the other of the two claw portions. An outer peripheral portion of the mounting portion has two outer peripheral notch portions. An inner peripheral portion of the mounting portion has two inner peripheral recessed portions.

Abstract: A semiconductor device includes: an insulating circuit substrate; a semiconductor element including a first main electrode bonded to a first conductor layer of the insulating circuit substrate via a first bonding material, a semiconductor substrate deposited on the first main electrode, and a second main electrode deposited on the semiconductor substrate; and a resistive element including a bottom surface electrode bonded to a second conductor layer of the insulating circuit substrate via a second bonding material, a resistive layer with one end electrically connected to the bottom surface electrode, and a top surface electrode electrically connected to another end of the resistive layer, wherein the first main electrode includes a first bonded layer bonded to the first bonding material, the bottom surface electrode includes a second bonded layer bonded to the second bonding material, and the first bonded layer and the second bonded layer have a common structure.

Abstract: A method performed during execution of a compilation process for a program having nested loops is provided. The method replaces multiple conditional branch instructions for a processor which uses a conditional branch instruction limited to only comparing a value of a general register with a value of a special register that holds a loop counter value. The method generates, in replacement of the multiple conditional branch instructions, the conditional branch instruction limited to only comparing the value of the general register with the value of the special register that holds the loop counter value for the inner-most loop. The method adds (i) a register initialization outside the nested loops and (ii) a register value adjustment to the inner-most loop. The method defines the value for the general register for the register initialization and conditions for the generated conditional branch instruction, responsive to requirements of the multiple conditional branch instructions.

Abstract: A device compresses a mapping table in a flash translation layer of a SSD. The mapping table includes mappings between Logical Page Numbers (LPNs) and Physical Page Numbers (PPNs). A base PPN table stores at least one entry including a base PPN common to multiple LPNs. A PPN offset table stores an offset for each mapping. A set of hash functions are duplicated for each entry in the base PPN table. A bit extension unit adds bits to the respective offset in the PPN offset table to provide an extended offset bit. A hash calculator calculates a hash value using the base PPN and one of the hash functions corresponding to the base PPN. An exclusive OR unit outputs a new PNN for each of different LPNs, including the multiple LPNs, by applying an exclusive OR operation to the hash value and the extended offset bit.

Abstract: A device compresses a mapping table in a flash translation layer of a SSD. The mapping table includes mappings between Logical Page Numbers (LPNs) and Physical Page Numbers (PPNs). A base PPN table stores at least one entry including a base PPN common to multiple LPNs. A PPN offset table stores an offset for each mapping. A set of hash functions are duplicated for each entry in the base PPN table. A bit extension unit adds bits to the respective offset in the PPN offset table to provide an extended offset bit. A hash calculator calculates a hash value using the base PPN and one of the hash functions corresponding to the base PPN. An exclusive OR unit outputs a new PNN for each of different LPNs, including the multiple LPNs, by applying an exclusive OR operation to the hash value and the extended offset bit.

Abstract: A method performed during execution of a compilation process for a program having nested loops is provided. The method replaces multiple conditional branch instructions for a processor which uses a conditional branch instruction limited to only comparing a value of a general register with a value of a special register that holds a loop counter value. The method generates, in replacement of the multiple conditional branch instructions, the conditional branch instruction limited to only comparing the value of the general register with the value of the special register that holds the loop counter value for the inner-most loop. The method adds (i) a register initialization outside the nested loops and (ii) a register value adjustment to the inner-most loop. The method defines the value for the general register for the register initialization and conditions for the generated conditional branch instruction, responsive to requirements of the multiple conditional branch instructions.

Abstract: To prevent an intermediate region from contacting a cathode electrode even if a cathode region is partially defective. There is provided a semiconductor device with a semiconductor substrate that has a field stop region where first impurities of a first conduction type are implanted, an intermediate region that is formed on a back surface side of the field stop region and where second impurities of a second conduction type are implanted, and a cathode region of the first conduction type that is formed on a back surface side of the intermediate region. In a back surface of the semiconductor substrate, a concentration of the first impurities is higher than a concentration of the second impurities.

Abstract: The position of the side wall of a metal electrode is precisely controlled and the coverage of a layer above the metal electrode is improved. A semiconductor device is provided, including: a semiconductor substrate; and a metal electrode formed above an upper surface of the semiconductor substrate, wherein a side wall of the metal electrode includes a lower portion contacting the semiconductor substrate, and an upper portion that is formed upper than the lower portion and has a smaller inclination relative to the upper surface of the semiconductor substrate than the lower portion. An active region formed in the semiconductor substrate is further included, and the metal electrode may be a field plate formed on an outer side relative to the active region on the upper surface of the semiconductor substrate. The upper portion of the side wall of the field plate may have an upward-convex shape.

Abstract: For enhancing a reverse-recovery immunity of a diode element, a semiconductor device includes a first conductivity-type drift layer, a second conductivity-type anode region provided in an upper portion of the drift layer, an insulating film provided on the drift layer, an anode electrode having an ohmic contact portion ohmically contacted to the anode region through a contact hole penetrating the insulating film, and a Schottky electrode Schottky-contacted to a peripheral portion of the anode region.

Abstract: For enhancing a reverse-recovery immunity of a diode element, a semiconductor device includes a first conductivity-type drift layer, a second conductivity-type anode region provided in an upper portion of the drift layer, an insulating film provided on the drift layer, an anode electrode having an ohmic contact portion ohmically contacted to the anode region through a contact hole penetrating the insulating film, and a Schottky electrode Schottky-contacted to a peripheral portion of the anode region.

Abstract: In a pin diode, a new means for a soft recovery other than the means for the soft recovery using an anode layer with a low concentration and a local lifetime control is provided. A semiconductor device comprising a drift layer of a first conductivity type provided on a semiconductor substrate of a first conductivity type, a front-surface-side region of a second conductivity type provided on a front surface side of the drift layer, an insulating-film layer provided on a front surface side of the front-surface-side region with a thickness thinner than a natural oxide film, and a metal layer provided on a front surface side of the insulating-film layer is provided.

Abstract: The position of the side wall of a metal electrode is precisely controlled and the coverage of a layer above the metal electrode is improved. A semiconductor device is provided, including: a semiconductor substrate; and a metal electrode formed above an upper surface of the semiconductor substrate, wherein a side wall of the metal electrode includes a lower portion contacting the semiconductor substrate, and an upper portion that is formed upper than the lower portion and has a smaller inclination relative to the upper surface of the semiconductor substrate than the lower portion. An active region formed in the semiconductor substrate is further included, and the metal electrode may be a field plate formed on an outer side relative to the active region on the upper surface of the semiconductor substrate. The upper portion of the side wall of the field plate may have an upward-convex shape.

Abstract: To prevent an intermediate region from contacting a cathode electrode even if a cathode region is partially defective. There is provided a semiconductor device with a semiconductor substrate that has a field stop region where first impurities of a first conduction type are implanted, an intermediate region that is formed on a back surface side of the field stop region and where second impurities of a second conduction type are implanted, and a cathode region of the first conduction type that is formed on a back surface side of the intermediate region. In a back surface of the semiconductor substrate, a concentration of the first impurities is higher than a concentration of the second impurities.

Abstract: To improve withstand capability of a semiconductor device during reverse recovery, provided is a semiconductor device including a semiconductor substrate having a first conduction type; a first region having a second conduction type that is formed in a front surface of the semiconductor substrate; a second region having a second conduction type that is formed adjacent to the first region in the front surface of the semiconductor substrate and has a higher concentration than the first region; a third region having a second conduction type that is formed adjacent to the second region in the front surface of the semiconductor substrate and has a higher concentration than the second region; an insulating film that covers a portion of the second region and the third region; and an electrode connected to the second region and the first region that are not covered by the insulating film.

Abstract: To improve withstand capability of a semiconductor device during reverse recovery, provided is a semiconductor device including a semiconductor substrate having a first conduction type; a first region having a second conduction type that is formed in a front surface of the semiconductor substrate; a second region having a second conduction type that is formed adjacent to the first region in the front surface of the semiconductor substrate and has a higher concentration than the first region; a third region having a second conduction type that is formed adjacent to the second region in the front surface of the semiconductor substrate and has a higher concentration than the second region; an insulating film that covers a portion of the second region and the third region; and an electrode connected to the second region and the first region that are not covered by the insulating film.

Abstract: For enhancing a reverse-recovery immunity of a diode element, a semiconductor device includes a first conductivity-type drift layer, a second conductivity-type anode region provided in an upper portion of the drift layer, an insulating film provided on the drift layer, an anode electrode having an ohmic contact portion ohmically contacted to the anode region through a contact hole penetrating the insulating film, and a Schottky electrode Schottky-contacted to a peripheral portion of the anode region.

Abstract: In a pin diode, a new means for a soft recovery other than the means for the soft recovery using an anode layer with a low concentration and a local lifetime control is provided. A semiconductor device comprising a drift layer of a first conductivity type provided on a semiconductor substrate of a first conductivity type, a front-surface-side region of a second conductivity type provided on a front surface side of the drift layer, an insulating-film layer provided on a front surface side of the front-surface-side region with a thickness thinner than a natural oxide film, and a metal layer provided on a front surface side of the insulating-film layer is provided.

Abstract: A p-type base region, in which an n+ emitter region is formed, and a p-type floating region are provided in a surface layer of one main surface of an n-type semiconductor substrate and are separated from each other by a trench. An emitter electrode is provided so as to cover the p-type floating region, with an interlayer insulating film interposed there between, and to come into contact with the p-type base region and the n+ emitter region. In the trench, two divided polysilicon electrodes are provided in regions that face each other, with a cavity, which is surrounded by an insulating film, interposed there between, and are arranged along both side walls of the trench and are connected to different electrodes. With this structure, it is possible to ensure the insulation between the polysilicon electrodes in the trench, to reduce stress, and to suppress an increase in gate capacitance.

Abstract: A p-type base region, in which an n+ emitter region is formed, and a p-type floating region are provided in a surface layer of one main surface of an n-type semiconductor substrate and are separated from each other by a trench. An emitter electrode is provided so as to cover the p-type floating region, with an interlayer insulating film interposed there between, and to come into contact with the p-type base region and the n+ emitter region. In the trench, two divided polysilicon electrodes are provided in regions that face each other, with a cavity, which is surrounded by an insulating film, interposed there between, and are arranged along both side walls of the trench and are connected to different electrodes. With this structure, it is possible to ensure the insulation between the polysilicon electrodes in the trench, to reduce stress, and to suppress an increase in gate capacitance.