Abstract: The present disclosure describes a wired communication device having media access control (MAC) circuitry and physical layer (PHY) circuitry. The MAC circuitry frames one or more data packets in accordance with a wired communication standard or protocol to provide one or more data frames. The one or more data frames include one or more packets that are separated by interpacket gaps (IPGs). The MAC circuitry selectively choses a duration of the IPGs to maintain an average IPG duration. The PHY circuitry encodes the one or more data frames in accordance with a line coding scheme that is efficiently represents different possible combinations for types of characters present in the one or more data frames.

Abstract: The present disclosure describes a wired communication device having media access control (MAC) circuitry and physical layer (PHY) circuitry. The MAC circuitry frames one or more data packets in accordance with a wired communication standard or protocol to provide one or more data frames. The one or more data frames include one or more packets that are separated by interpacket gaps (IPGs). The MAC circuitry selectively choses a duration of the IPGs to maintain an average IPG duration. The PHY circuitry encodes the one or more data frames in accordance with a line coding scheme that is efficiently represents different possible combinations for types of characters present in the one or more data frames.

Abstract: A network device for processing packets. The network device includes applying specific fields from a packet to an associated memory device and comparing means for comparing input to the memory device with entries in the memory device. The network device also includes enabling means for enabling selection of bits, by the memory device, that are required to match exactly with bits from the input to the memory device. The network device further includes outputting means for outputting an address for a matched entry by the memory device and applying means for applying a match from the memory device to an associated entry in a table for applying actions from the table that are associated with the match to the packet.

Abstract: A network device for processing packets. The network device includes an ingress module for performing switching functions on an incoming packet. The network device also includes a memory management unit for storing packets and performing resource checks on each packet and an egress module for performing packet modification and transmitting the packet to an appropriate destination port. Each of the ingress module, memory management unit and egress module includes multiple cycles for processing instructions and each of the ingress module, memory management unit and egress module processes one packet every clock cycle.

Abstract: A network device for processing packets. The network devices includes a ingress module for performing lookups for layer 2 switching and performing operations for maintaining a layer 2 table. When the ingress module updates the layer 2 table, the ingress module records the operation performed on the layer 2 table in a modification buffer. Entries are added to the modification buffer when the layer 2 table is modified and in the order in which the layer 2 table was modified. The network device thus enables reconstruction of the layer 2 table by performing the operations in the modification buffer.

Abstract: An example network device includes a processor that is configured to apply specific fields from a packet to an associated memory device and comparing means for comparing input to the memory device with entries in the memory device. The example network device is configured to enable selection of bits, by the memory device, that are required to match exactly with bits from the input to the memory device. The specific fields include a plurality of fields some of which include multiple field values and definitions. An input bit map field of one of the plurality of fields is used to provide an additional global mask that is ANDed to associated masks in selected entries in the memory device thereby enabling the memory device to output an OR of the data in the selected entries and thereby allowing multiple ports to share a rule within a memory device entry.

Abstract: A method of handling a datagram in a network device is disclosed. The steps include receiving a datagram, with the datagram having multiple field values, at a port of a network device, parsing the received datagram to obtain the field values, applying the parsed field values to a Ternary Content Addressable Memory (TCAM), determining matches between the parsed field values and predetermined criteria in the TCAM, indexing into a policy table based on the determined matches to obtain an action entry and taking an action based on the obtained action entry.

Abstract: A network device for processing packets. The network devices includes a ingress module for performing lookups for layer 2 switching and performing operations for maintaining a layer 2 table. When the ingress module updates the layer 2 table, the ingress module records the operation performed on the layer 2 table in a modification buffer. Entries are added to the modification buffer when the layer 2 table is modified and in the order in which the layer 2 table was modified. The network device thus enables reconstruction of the layer 2 table by performing the operations in the modification buffer.

Abstract: A network device for processing packets. The network devices includes a ingress module for performing lookups for layer 2 switching and performing operations for maintaining a layer 2 table. When the ingress module updates the layer 2 table, the ingress module records the operation performed on the layer 2 table in a modification buffer. Entries are added to the modification buffer when the layer 2 table is modified and in the order in which the layer 2 table was modified. The network device thus enables reconstruction of the layer 2 table by performing the operations in the modification buffer.

Abstract: A network device for processing packets. The network device includes applying specific fields from a packet to an associated memory device and comparing means for comparing input to the memory device with entries in the memory device. The network device also includes enabling means for enabling selection of bits, by the memory device, that are required to match exactly with bits from the input to the memory device. The network device further includes outputting means for outputting an address for a matched entry by the memory device and applying means for applying a match from the memory device to an associated entry in a table for applying actions from the table that are associated with the match to the packet.

Abstract: A system includes a requesting agent coupled to a system bus. The system bus includes an address bus, control lines for indicating a requested transfer type, a data bus, address bus arbitration control lines and data bus arbitration control lines. The system further includes a system bus arbiter coupled to the system bus for resolving competing requests for access to the address bus and for separately resolving competing requests for access to the data bus. A graphics controller for enabling the requesting agent to access a frame buffer has a memory, which may be a FIFO, responsive to a first control signal, for storing data received from a frame buffer. The memory is further responsive to a second control signal for supplying the stored data to the data bus. The graphics controller also includes a controller coupled to the system bus and to the memory means.

Abstract: In a computer system an apparatus interconnects a first bus, a second bus and a frame buffer, wherein the first bus and the second bus are of incompatible bus architecture types. For example the first bus may be a loosely coupled bus having split-bus transaction capability, such as the ARBus, and the second bus may be a tightly ordered bus, such as the PCI local bus. The apparatus includes bridge hardware for converting access requests from the first bus into suitable requests for the second bus. Data paths within the apparatus allow data to be routed from one bus to another. The apparatus further includes a frame buffer controller that is accessible from either of the first or second buses for performing read or write operations from/to the frame buffer. Data path logic allows data to be routed from any of the first bus, second bus and frame buffer to any other one of these three locations.

Abstract: A method of prioritizing computer resource access requests to a shared computer resource, such as a video frame buffer, includes the steps of providing a number, n, of priority schemes in correspondence with a like number of potentially requesting entities, where n is an integer greater than one, and where each priority scheme designates relative priority of the potentially requesting entities with respect to one another. Thus, for each priority scheme there exists one corresponding potentially requesting entity, and a number, n-1, of noncorresponding potentially requesting entities. Next, one of the priority schemes is selected for use as a current priority scheme. A set of currently requesting entities is then determined from the number of potentially requesting entities, and the current priority scheme is used to select a highest priority requesting entity from the set of currently requesting entities.

Abstract: An apparatus for transforming pixel data from a data bus into an expected format for storage in a frame buffer has a first multiplexor, a second multiplexor and a controller. The first multiplexor includes two data inputs coupled to the data bus so that the first data input provides pass-through of received data, and the second data input provides end-for-end byte swapping of bus data. Input selection is made by a byte-swap control signal. The second multiplexor includes an output and four data inputs. The output of the first multiplexor is coupled to each of the four inputs of the second multiplexor so as to provide for end-for-end byte swapping from two of the inputs, end-for-end word swapping from another one of the inputs, and end-for-end half-word swapping from a fourth input. The second multiplexor is responsive to a reorder control signal that alternatively selects one of the first, second, third and fourth inputs of the second multiplexor to be gated to the output of the second multiplexor.

Abstract: A computer bus bridge interconnects first and second buses, the first bus being big-endian and the second bus being little-endian. First address and size signals received from the first bus during a first bus cycle are converted into second address and data unit enable signals for transmission on the second bus during a second bus cycle. The first address comprises a low-order address portion and a remaining upper-order address portion. The data unit enable signals are generated from the low-order address portion and the size signals of the first bus. An address offset is generated from the data unit enable signals. The remaining upper-order address portion of the first address are then concatenated with the address offset and a predetermined lower address portion for use as the second address. The data unit enable signals may designate, say, up to 4 possible data bytes being transferred during a single beat on the second bus.

Abstract: A system has a system resource, such as a frame buffer, coupled to a system bus, the system bus conveying a request for access to the system resource from another system element connected to the system bus. An apparatus for presenting the access request to the system resource from the system bus includes a queue, a multiplexor that is preferably glitchless, and a controller. The queue has an input for receiving access request information from the system bus; one or more storage elements, each for storing access request information, wherein the one or more storage means are connected to form a queue having a head and a tail; and a queue output for supplying data stored in the head of the queue. The multiplexor has a first input coupled to the queue output, a second input for receiving the access request information from the system bus, and a multiplexor output for supplying the access request to the system resource.

Abstract: The present invention reduces the overhead commonly associated with computer queues by not requiring direct addressing of each location in the queue and by not requiring specialized underflow logic. Furthermore, reads and writes to the computer queue of the present invention can be asynchronous. Lastly, the computer queue of the present invention requires less circuitry and is thus physically smaller, requires less power to operate and can operate more quickly than can queues of the prior art.