Abstract: A semiconductor structure includes a plurality of mandrel structures disposed above and in contact with a substrate. Each of the plurality of mandrel structures extending outwardly at an inclination angle with respect to a surface plane of the substrate that is different from 90 degrees. A template structure for an imprint mask is formed by the plurality of mandrel structures. The semiconductor structure further includes a layer of a conformal dielectric material covering the plurality of mandrel structures for providing stability and uniformity to the plurality of mandrel structures.

Abstract: A semiconductor structure includes a first plurality of slanted features within a first region of a substrate. Two or more magnetic guiding structures are embedded within the first region of the substrate. The first plurality of slanted features is located between the two or more magnetic guiding structures for varying a magnetic field strength around the first plurality of slanted features. A second plurality of slanted features are located within a second region of the substrate. The second region of the substrate is adjacent to the first region of the substrate. The second plurality of slanted features include a second orientation angle that is different from a first orientation angle of the first plurality of slanted features.

Abstract: A porous thin film includes a framework that includes a plurality of pores. The pores extend from an opening located at an upper surface of the framework to a bottom surface contained in the framework. A pore-coating film is formed on sidewalls and the bottom surface of the pores.

Abstract: A porous thin film includes a framework that includes a plurality of pores. The pores extend from an opening located at an upper surface of the framework to a bottom surface contained in the framework. A pore-coating film is formed on sidewalls and the bottom surface of the pores.

Abstract: Integrated circuits including at least two electrically conductive interconnect lines and methods of manufacturing generally include a surface of the integrated circuit. At least two electrically conductive interconnect lines are separated by a space of less than 90 nm and are formed on the surface. Each of the at least two interconnect lines includes a metal cap, a copper conductor having an average grain size greater than a line width of the interconnect. A liner layer is provided, wherein the liner layer and the metal cap encapsulate the copper conductor. A dielectric layer overlaying the at least two electrically conductive interconnect lines and extending along sidewalls thereof is provided, wherein the dielectric layer is configured to provide an airgap between the at least two interconnect lines at the spacing.

Abstract: The present disclosure relates to integrated circuits and to methods of manufacturing interconnects of integrated circuits. For example, an integrated circuit includes a surface of the integrated circuit and an interconnect formed on the surface and comprising a metal. An average grain size of the metal of the interconnect is greater than or equal to at least half of a line width of the interconnect. In another example, a method for manufacturing an interconnect of an integrated circuit includes depositing a layer of a metal onto a surface of the integrated circuit, annealing the metal, patterning a first hard mask for placement over the metal and forming a line of the interconnect and a first via of the interconnect by performing a timed etch of the metal using the first hard mask.

Abstract: In one embodiment, a method for hydrofluorocarbon gas-assisted plasma etch for interconnect fabrication includes providing a layer of a dielectric material and etching a trench in the layer of the dielectric material, by applying a mixture of an aggressive dielectric etch gas and a polymerizing etch gas to the layer of the dielectric material. In another embodiment, an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices. A pitch of the plurality of conductive lines is approximately twenty-eight nanometers.

Abstract: An apparatus for and methods of repairing and manufacturing integrated circuits using the apparatus. The apparatus, comprising: a vacuum chamber containing: a movable stage configured to hold a substrate; an inspection and analysis probe; a heat source; a gas injector; and a gas manifold connecting multiple gas sources to the gas injector.

Abstract: A process for forming patterned copper lines, a pattern of copper lines, and an electronic device having patterned copper lines and at least one CMOS circuit. The process includes assembling an etch stack, wherein the etch stack includes a resist and a copper substrate. The process also includes lithographically patterning the resist to produce a template, and forming a patterned block copolymer mask layer by directed self-assembly. Additionally, the process includes etching portions of the block copolymer mask layer to produce a patterned block copolymer mask layer, and transferring a pattern formed by the template and the patterned block copolymer mask layer to the copper substrate to form the patterned copper lines.

Abstract: A method of forming integrated circuit (IC) chips. After masking a layer of a material to be etched, the layer is subjected to an atomic layer etch (ALE). During the ALE, etch effluent is measured with a calorimetric probe. The calorimetric probe results reflect a species of particles resulting from etching the material. The measured etch results are checked until the results indicate the particle content is below a threshold value. When the content is below the threshold ALE is complete and IC chip fabrication continues normally.

Abstract: A magnetoresistive memory cell includes a magnetic tunnel junction pillar having a circular cross section. The pillar has a pinned magnetic layer, a tunnel barrier layer, and a free magnetic layer. A first conductive contact is disposed above the magnetic tunnel junction pillar. A second conductive contact is disposed below the magnetic tunnel junction pillar.

Abstract: A method of forming integrated circuit (IC) chips. After masking a layer of a material to be etched, the layer is subjected to an atomic layer etch (ALE). During the ALE, etch effluent is measured with a calorimetric probe. The calorimetric probe results reflect a species of particles resulting from etching the material. The measured etch results are checked until the results indicate the particle content is below a threshold value. When the content is below the threshold ALE is complete and IC chip fabrication continues normally.

Abstract: A process for forming patterned copper lines, a pattern of copper lines, and an electronic device having patterned copper lines and at least one CMOS circuit. The process includes assembling an etch stack, wherein the etch stack includes a resist and a copper substrate. The process also includes lithographically patterning the resist to produce a template, and forming a patterned block copolymer mask layer by directed self-assembly. Additionally, the process includes etching portions of the block copolymer mask layer to produce a patterned block copolymer mask layer, and transferring a pattern formed by the template and the patterned block copolymer mask layer to the copper substrate to form the patterned copper lines.

Abstract: The present disclosure relates to integrated circuits and to methods of manufacturing interconnects of integrated circuits. For example, an integrated circuit includes a surface of the integrated circuit and an interconnect formed on the surface and comprising a metal. An average grain size of the metal of the interconnect is greater than or equal to at least half of a line width of the interconnect. In another example, a method for manufacturing an interconnect of an integrated circuit includes depositing a layer of a metal onto a surface of the integrated circuit, annealing the metal, patterning a first hard mask for placement over the metal and forming a line of the interconnect and a first via of the interconnect by performing a timed etch of the metal using the first hard mask.

Abstract: In one example, a method for fabricating an integrated circuit includes patterning a layer of a first conductive metal, via a subtractive etch process, to form a plurality of lines for connecting semiconductor devices on the integrated circuit. A large feature area is formed outside of the plurality of conductive lines via a metal fill process using a second conductive metal.

Abstract: In one embodiment, a method for hydrofluorocarbon gas-assisted plasma etch for interconnect fabrication includes providing a layer of a dielectric material and etching a trench in the layer of the dielectric material, by applying a mixture of an aggressive dielectric etch gas and a polymerizing etch gas to the layer of the dielectric material. In another embodiment, an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices. A pitch of the plurality of conductive lines is approximately twenty-eight nanometers.

Abstract: The present disclosure relates to integrated circuits and to methods of manufacturing interconnects of integrated circuits. For example, an integrated circuit includes a surface of the integrated circuit and an interconnect formed on the surface and comprising a metal. An average grain size of the metal of the interconnect is greater than or equal to at least half of a line width of the interconnect. In another example, a method for manufacturing an interconnect of an integrated circuit includes depositing a layer of a metal onto a surface of the integrated circuit, annealing the metal, patterning a first hard mask for placement over the metal and forming a line of the interconnect and a first via of the interconnect by performing a timed etch of the metal using the first hard mask.

Abstract: A method of forming a pillar includes masking a photoresist material using a reticle and a developer having a polarity opposite that of the photoresist to provide an island of photoresist material. A layer under the island of photoresist material is etched to establish a pillar defined by the island of photoresist material.

Abstract: A method for cleaning etch residues that may include treating an etched surface with an aqueous lanthanoid solution, wherein the aqueous lanthanoid solution removes an etch residue that includes a majority of hydrocarbons and at least one element selected from the group consisting of carbon, oxygen, fluorine, nitrogen and silicon. In one example, the aqueous solution may be cerium ammonium nitrate (Ce(NH4)(NO3)),(CAN).

Abstract: In one example, a method for fabricating an integrated circuit includes patterning a layer of a first conductive metal, via a subtractive etch process, to form a plurality of lines for connecting semiconductor devices on the integrated circuit. A large feature area is formed outside of the plurality of conductive lines via a metal fill process using a second conductive metal.