Abstract: Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.

Abstract: An electrocardiogram device configured to transmit at least one signal responsive to a wearer's cardiac electrical activity can include a disposable portion and a reusable portion configured to mechanically and electrically mate with each other. The disposable portion can include a base having at least one mechanical connector portion, a plurality of cables and corresponding external ECG electrodes, and a first plurality of electrical connectors associated with the plurality of cables. The reusable portion can include a cover having at least one mechanical connector portion, a second plurality of electrical connectors configured to electrically connect with the first plurality of electrical connectors of the disposable portion, and an output connector port configured to transmit at least one signal responsive to one or more signals outputted by the external ECG electrodes of the disposable portion.

Abstract: A device for obtaining physiological information of a medical patient and wirelessly transmitting the obtained physiological information to a wireless receiver.

Abstract: A device for obtaining physiological information of a medical patient and wirelessly transmitting the obtained physiological information to a wireless receiver.

Abstract: Quantum dot devices with three of more accumulation gates provided over a single row of a quantum dot formation region are disclosed. Each accumulation gate is electrically coupled to a respective doped region. In this manner, multiple single electron transistors (SETs) are provided along the row. Side and/or center screening gates may be used to apply microwave pulses for qubit control and to control electrostatics so that source and drain regions of the multiple SETs with quantum dots formed along the single row of a quantum dot formation region are sufficiently isolated from one another. Such quantum dot devices provide strong spatial localization of the quantum dots, good control over quantum dot interactions and manipulation, good scalability in the number of quantum dots included in the device, and/or design flexibility in making electrical connections to the quantum dot devices to integrate the quantum dot devices in larger computing devices.

Abstract: An actuator system includes an actuator with a deformable shell defining a pouch, a fluid dielectric contained within the pouch, and first and second electrodes disposed over opposing sides of the pouch, each electrode having two long edges and two short edges. The system also includes a power source for providing a voltage between the electrodes. The electrodes cover 50 to 90% of the first and second sides, respectively, of the pouch, and a gap is defined between long edges of the pouch and the electrodes such that, upon application of the voltage at one of the short edges of the electrodes, respectively, the electrodes selectively zip together from the one of the short edges toward an opposing one of the short edges. The system may also include a support structure for enabling the actuator to maintain its shape regardless of the voltage provided by the power source.

Abstract: A uterine fibroid tissue removal device includes an inner tube disposed within an outer tube and configured to be translated and rotated relative to the outer tube, and a separately formed unitary distal tip member attached to a distal end of the inner tube, such that the distal tip member translates and rotates relative to the outer tube along with the inner tube, wherein a distal facing open cutting end of the distal tip member in fluid communication with an axial lumen of the distal tip member translates across a tissue resection window in a sidewall of the outer tube so as to sever tissue extending therethrough, the distal tip member axial lumen being in fluid communication with an axial lumen of the inner tube, wherein an outer diameter of the distal tip member is greater than an outer diameter of the inner tube.

Abstract: The present disclosure includes a medical monitoring hub as the center of monitoring for a monitored patient. The hub includes configurable medical ports and serial ports for communicating with other medical devices in the patient's proximity. Moreover, the hub communicates with a portable patient monitor. The monitor, when docked with the hub provides display graphics different from when undocked, the display graphics including anatomical information. The hub assembles the often vast amount of electronic medical data, associates it with the monitored patient, and in some embodiments, communicates the data to the patient's medical records.

Abstract: A medical device may include an expandable energy delivery array reciprocally movable between a first configuration and a second configuration. The expandable energy delivery array may include a first assembly having a first proximal end piece, a first distal end piece, and one or more first energy transfer elements extending between the first proximal and first distal end pieces, and a second assembly having a second proximal end piece, a second distal end piece, and one or more second energy transfer elements extending between the second proximal and second distal end pieces. The second proximal end piece may be proximal to the first proximal end piece and the second distal end piece may be distal to the first distal end piece.

Abstract: The present disclosure includes a medical monitoring hub as the center of monitoring for a monitored patient. The hub includes configurable medical ports and serial ports for communicating with other medical devices in the patient's proximity. Moreover, the hub communicates with a portable patient monitor. The monitor, when docked with the hub provides display graphics different from when undocked, the display graphics including anatomical information. The hub assembles the often vast amount of electronic medical data, associates it with the monitored patient, and in some embodiments, communicates the data to the patient's medical records.

Abstract: Uniform layouts for SRAM and register file bit cells are described. In an example, an integrated circuit structure includes a six transistor (6T) static random access memory (SRAM) bit cell on a substrate. The 6T SRAM bit cell includes first and second active regions parallel along a first direction of the substrate. First, second, third and fourth gate lines are over the first and second active regions, the first, second, third and fourth gate lines parallel along a second direction of the substrate, the second direction perpendicular to the first direction.

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and techniques directed to electrical couplings between epitaxial structures and voltage sources within transistors in SRAM bit cells. Embodiments include direct electrical couplings between a backside contact metal (BM0) and a backside of an epitaxial structure, as well as electrical connection structures that electrically couple the BM0 to a front side of an epitaxial structure. Other embodiments may be described and/or claimed.

Abstract: Uniform layouts for SRAM and register file bit cells are described. In an example, an integrated circuit structure includes a six transistor (6T) static random access memory (SRAM) bit cell on a substrate. The 6T SRAM bit cell includes first and second active regions parallel along a first direction of the substrate. First, second, third and fourth gate lines are over the first and second active regions, the first, second, third and fourth gate lines parallel along a second direction of the substrate, the second direction perpendicular to the first direction.

Abstract: Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.

Abstract: Integrated circuit (IC) static random-access memory (SRAM) comprising pass-gate transistors and pull-down transistors having different threshold voltages (Vt). A pass-gate transistor with a higher Vt than the pull-down transistor, may reduce read instability of a bit-cell, and/or reduce overhead associated with read assist circuitry coupled to the bit-cell. In some examples, a different amount of a dipole dopant source material is deposited as part of the gate insulator for the pull-down transistor than for the pass-gate transistor, reducing the Vt of the pull-down transistor accordingly. In some examples, an N-dipole dopant source material is removed from the pass-gate transistor prior to a drive/activation anneal is performed. After drive/activation, the N-dipole dopant source material may be removed from the pull-down transistor and a same gate metal deposited over both the pass-gate and pull-down transistors.

Abstract: Integrated circuit (IC) static random-access memory (SRAM) comprising colinear pass-gate transistors and pull-down transistors having different nanoribbon widths. A narrower ribbon width within the pass-gate transistor, relative to the pull-down transistor, may reduce read instability of a bit-cell, and/or reduce overhead associated with read assist circuitry coupled to the bit-cell. In some examples, a transition between narrower and width ribbon widths is symmetrical about a centerline shared by ribbons of both the access and pull-down transistors. In some examples, the ribbon width transition is positioned within an impurity-doped semiconductor region shared by the access and pull-down transistors and may be located under a terminal contact metallization. In some examples, the impurity-doped semiconductor regions surrounding the ribbons of differing width also have differing widths.

Abstract: Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.

Abstract: A sensor device having a sensor housing and a printed circuit board coupled to the sensor housing. A light emitting device is coupled to the printed circuit board. The light emitting device has an emitter face defining an emission face area. An aperture plate is coupled to the sensor housing, the aperture plate defines an aperture having an aperture area that is less than the emission face area of the emitter face. The aperture is less than 1 mm from the emitter face wherein the light emitting device is not fixed to the aperture plate. A lens is coupled to the sensor housing, having an optical axis extending through the aperture. The aperture plate is positioned between the lens and the emitter face. Boresighting angle variation across sensor components on a manufacturing line may advantageously be reduced without increased cost associated with active alignment. Irradiance drop-out may also be reduced.

Abstract: A system for non-invasively determining an indication of an individual's blood pressure is described. In certain embodiments, the system calculates pulse wave transit time using two acoustic sensors. The system can include a first acoustic sensor configured to monitor heart sounds of the patient corresponding to ventricular systole and diastole and a second acoustic sensor configured to monitor arterial pulse sounds at an arterial location remote from the heart. The system can advantageously calculate a arterial pulse wave transit time (PWTT) that does not include the pre-ejection period time delay. In certain embodiments, the system further includes a processor that calculates the arterial PWTT obtained from the acoustic sensors. The system can use this arterial PWTT to determine whether to trigger an occlusive cuff measurement.

Abstract: An analog multiplication circuit includes switched capacitors to multiply digital operands in an analog representation and output a digital result with an analog-to-digital convertor. The capacitors are arranged with a capacitance according to the respective value of the digital bit inputs. To perform the multiplication, the capacitors are selectively charged according to the first operand of the multiplication. The capacitors are then connected to a common interconnect for charge sharing across the capacitors, averaging the charge according to the charge determined by the first operand. The capacitor are then maintained or discharged according to a second operand, such that the remaining charge represents a number of “copies” of the averaged charge. The capacitors are then averaged and output for conversion by an analog-to-digital convertor. This circuit may be repeated to construct a multiply-and-accumulate circuit by combining charges from several such multiplication circuits.