Patents by Inventor Eric A. Lehner

Eric A. Lehner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5897982
    Abstract: A resist develop process involves the steps of dispensing a developer on a resist on a semiconductor wafer, forming the developer into a puddle where a portion of the resist dissolves into the developer, dispensing additional developer following development, rinsing the wafer with a rinsing agent, and drying the wafer surface. The additional developer dispense step replaces developer with resist dissolved therein with new developer prior to the rinsing step to prevent potential resist precipitation during the rinsing step which can lead to bridging.
    Type: Grant
    Filed: March 5, 1996
    Date of Patent: April 27, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsuyoshi Shibata, Eric A. Lehner
  • Patent number: 5318877
    Abstract: A resist pattern on a substrate is formed using an imageable resist layer on the surface of a substrate. The imageable resist layer comprises a silicon-incorporated polystyrene-diene block copolymer having a silicon weight percent of at least about 5 percent. The imageable layer is prepared by reacting a polystyrene-diene block copolymer with a silicon-containing compound in the presence of a platinum catalyst. In a preferred embodiment, the poly(styrene)-diene block copolymers are hydrosilylated by hydrosiloxanes using a platinum-divinyl tetramethyl disiloxane catalyst.
    Type: Grant
    Filed: November 22, 1993
    Date of Patent: June 7, 1994
    Assignee: Cornell Research Foundation, Inc.
    Inventors: Christopher K. Ober, Allen H. Gabor, Eric A. Lehner, Guoping Mao, Lizabeth A. Schneggenburger
  • Patent number: 5290397
    Abstract: A resist pattern on a substrate is formed using an imageable resist layer on the surface of a substrate. The imageable resist layer comprises a silicon-incorporated polystyrene-diene block copolymer having a silicon weight percent of at least about 5 percent. The imageable layer is prepared by reacting a polystyrene-diene block copolymer with a silicon-containing compound in the presence of a platinum catalyst. In a preferred embodiment, the poly(styrene)-diene block copolymers are hydrosilylated by hydrosiloxanes using a platinum-divinyl tetramethyl disiloxane catalyst.
    Type: Grant
    Filed: August 21, 1992
    Date of Patent: March 1, 1994
    Assignee: Cornell Research Foundation, Inc.
    Inventors: Christopher K. Ober, Allen H. Gabor, Eric A. Lehner, Guoping Mao, Lizabeth A. Schneggenburger