Abstract: A polyphase harmonic rejection mixer, comprising a plurality of stages following each other; wherein a first stage is arranged to perform at least frequency conversion; and a second stage is arranged to perform at least selective weighting and combining; wherein at least two of the plurality of stages are arranged to perform at least combining. In an embodiment, the first stage (28) comprises three single-ended gain blocks (10, 12, 14), arranged to perform selective weighting, frequency conversion and combining; and a second stage (30) following the first stage (28) and arranged to perform selective weighting and combining. The second stage (30) may reduce the number of phases output by the first stage (28) and may output (32) a complex differential down converted signal. The mixer may be directly interfaced to an antenna of an LNA-less receiver without weighting in the first stage. The mixer may be included in a software-defined radio.

Abstract: A polyphase harmonic rejection mixer, comprising a plurality of stages following each other; wherein a first stage is arranged to perform at least frequency conversion; and a second stage is arranged to perform at least selective weighting and combining; wherein at least two of the plurality of stages are arranged to perform at least combining. In an embodiment, the first stage (28) comprises three single-ended gain blocks (10, 12, 14), arranged to perform selective weighting, frequency conversion and combining; and a second stage (30) following the first stage (28) and arranged to perform selective weighting and combining. The second stage (30) may reduce the number of phases output by the first stage (28) and may output (32) a complex differential down converted signal. The mixer may be directly interfaced to an antenna of an LNA-less receiver without weighting in the first stage. The mixer may be included in a software-defined radio.

Abstract: Phase-locked loop (PLL) circuitry in which a sampling phase detector samples the output signal in accordance with the reference signal and a frequency detector detects the output signal frequency in accordance with the reference signal.

Abstract: A linear-gain amplifier arrangement comprises a current amplifying cell consisting of field-effect transistors and comprising a first (M1, M3) and a second (M2, M4current-mirror circuit whose respective input transistors (M1; M2) and output transistors (M3; M4) constitute a first and a second differential pair. The input transistors (M1; M2) have their drain electrodes connected to voltage-current converter (V/I) made up of field-effect transistors. The V/I converter supplies difference currents (I.sub.in1 ; I.sub.in2) which are square-law functions of the input voltage (U.sub.in) to be amplified. The difference between these input currents is a linear function of the input voltage. When the transistors are operated in their saturation regions the difference between the output currents (I.sub.out1 ; I.sub.out2) is also a linear function of the input voltage (U.sub.in). By adding a direct voltage (V.sub.c) to the gate-source voltage of the input and output transistors or by adding a direct current (I.sub.