Patents by Inventor Eric A. Sprangle

Eric A. Sprangle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Distribution of tasks among asymmetric processing elements
    Patent number: 11366511
    Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: June 21, 2022
    Assignee: Intel Corporation
    Inventors: Herbert Hum, Eric Sprangle, Doug Carmean, Rajesh Kumar
  • Distribution of tasks among asymmetric processing elements
    Patent number: 11054890
    Abstract: Techniques to control power and processing among a plurality of asymmetric processing elements are disclosed. In one embodiment, one or more asymmetric processing elements are power managed to migrate processes or threads among a plurality of processing elements according to the performance and power needs of the system.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: July 6, 2021
    Assignee: Intel Corporation
    Inventors: Herbert Hum, Eric Sprangle, Doug Carmean, Rajesh Kumar
  • DISTRIBUTION OF TASKS AMONG ASYMMETRIC PROCESSING ELEMENTS
    Publication number: 20210089113
    Abstract: Techniques to control power and processing among a plurality of asymmetric cores.
    Type: Application
    Filed: December 8, 2020
    Publication date: March 25, 2021
    Applicant: Intel Corporation
    Inventors: Herbert Hum, Eric Sprangle, Doug Carmean, Rajesh Kumar
  • Distribution of tasks among asymmetric processing elements
    Patent number: 10437320
    Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: October 8, 2019
    Assignee: Intel Corporation
    Inventors: Herbert Hum, Eric Sprangle, Doug Carmean, Rajesh Kumar
  • Distribution of tasks among asymmetric processing elements
    Patent number: 10409360
    Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: September 10, 2019
    Assignee: Intel Corporation
    Inventors: Herbert Hum, Eric Sprangle, Doug Carmean, Rajesh Kumar
  • Distribution of tasks among asymmetric processing elements
    Patent number: 10386915
    Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: August 20, 2019
    Assignee: Intel Corporation
    Inventors: Herbert Hum, Eric Sprangle, Doug Carmean, Rajesh Kumar
  • Sharing resources between a CPU and GPU
    Patent number: 10181171
    Abstract: A technique to share execution resources. In one embodiment, a CPU and a GPU share resources according to workload, power considerations, or available resources by scheduling or transferring instructions and information between the CPU and GPU.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: January 15, 2019
    Assignee: Intel Corporation
    Inventors: Eric Sprangle, Matt Craighead, Chris Goodman, Belliappa Kuttanna
  • System and method for using a mask register to track progress of gathering and scattering elements between data registers and memory
    Patent number: 10042814
    Abstract: A device, system and method for assigning values to elements in a first register, where each data field in a first register corresponds to a data element to be written into a second register, and where for each data field in the first register, a first value may indicate that the corresponding data element has not been written into the second register and a second value indicates that the corresponding data element has been written into the second register, reading the values of each of the data fields in the first register, and for each data field in the first register having the first value, gathering the corresponding data element and writing the corresponding data element into the second register, and changing the value of the data field in the first register from the first value to the second value. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: August 7, 2018
    Assignee: Intel Corporation
    Inventors: Eric Sprangle, Anwar Rohillah, Robert Cavin, Andrew T. Forsyth, Michael Abrash
  • Systems and methods for migrating processes among asymmetrical processing cores
    Patent number: 9939882
    Abstract: Techniques to control power and processing among a plurality of asymmetric processing elements are disclosed. In one embodiment, one or more asymmetric processing elements are power managed to migrate processes or threads among a plurality of processing elements according to the performance and power needs of the system.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: April 10, 2018
    Assignee: Intel Corporation
    Inventors: Herbert Hum, Eric Sprangle, Doug Carmean, Rajesh Kumar
  • Distribution of tasks among asymmetric processing elements
    Patent number: 9910483
    Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: March 6, 2018
    Assignee: Intel Corporation
    Inventors: Herbert Hum, Eric Sprangle, Doug Carmean, Rajesh Kumar
  • Distribution of tasks among asymmetric processing elements
    Patent number: 9874926
    Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: January 23, 2018
    Assignee: Intel Corporation
    Inventors: Herbert Hum, Eric Sprangle, Douglas Carmean, Rajesh Kumar
  • Distribution of tasks among asymmetric processing elements
    Patent number: 9870046
    Abstract: Techniques to control power and processing among a plurality of asymmetric processing elements are disclosed.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: January 16, 2018
    Assignee: Intel Corporation
    Inventors: Herbert Hum, Eric Sprangle, Doug Carmean, Rajesh Kumar
  • Distribution of tasks among asymmetric processing elements
    Patent number: 9829965
    Abstract: Techniques are disclosed to control power and processing among a plurality of asymmetric cores.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: November 28, 2017
    Assignee: Intel Corporation
    Inventors: Herbert Hum, Eric Sprangle, Douglas Carmean, Rajesh Kumar
  • Super multiply add (super MADD) instructions with three scalar terms
    Patent number: 9792115
    Abstract: A processing core is described having execution unit logic circuitry having a first register to store a first vector input operand, a second register to a store a second vector input operand and a third register to store a packed data structure containing scalar input operands a, b, c. The execution unit logic circuitry further include a multiplier to perform the operation (a*(first vector input operand))+(b*(second vector operand))+c.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Jesus Corbal, Andrew T. Forsyth, Thomas D. Fletcher, Lisa K. Wu, Eric Sprangle
  • Distribution of tasks among asymmetric processing elements
    Patent number: 9760162
    Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: September 12, 2017
    Assignee: Intel Corporation
    Inventors: Herbert Hum, Eric Sprangle, Doug Carmean, Rajesh Kumar
  • Distribution of tasks among asymmetric processing elements
    Patent number: 9753530
    Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: September 5, 2017
    Assignee: Intel Corporation
    Inventors: Herbert Hum, Eric Sprangle, Douglas Carmean, Rajesh Kumar
  • Distribution of Tasks Among Asymmetric Processing Elements
    Publication number: 20170024001
    Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.
    Type: Application
    Filed: September 2, 2016
    Publication date: January 26, 2017
    Inventors: HERBERT HUM, ERIC SPRANGLE, DOUG CARMEAN, RAJESH KUMAR
  • Distribution of Tasks Among Asymmetric Processing Elements
    Publication number: 20160370852
    Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.
    Type: Application
    Filed: September 2, 2016
    Publication date: December 22, 2016
    Inventors: HERBERT HUM, ERIC SPRANGLE, DOUG CARMEAN, RAJESH KUMAR
  • Distribution of Tasks Among Asymmetric Processing Elements
    Publication number: 20160370851
    Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.
    Type: Application
    Filed: September 2, 2016
    Publication date: December 22, 2016
    Inventors: HERBERT HUM, ERIC SPRANGLE, DOUG CARMEAN, RAJESH KUMAR
  • Methods, apparatus, and instructions for converting vector data
    Patent number: 9495153
    Abstract: A computer processor includes a decoder for decoding machine instructions and an execution unit for executing those instructions. The decoder and the execution unit are capable of decoding and executing vector instructions that include one or more format conversion indicators. For instance, the processor may be capable of executing a vector-load-convert-and-write (VLoadConWr) instruction that provides for loading data from memory to a vector register. The VLoadConWr instruction may include a format conversion indicator to indicate that the data from memory should be converted from a first format to a second format before the data is loaded into the vector register. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 15, 2016
    Assignee: Intel Corporation
    Inventors: Eric Sprangle, Robert D. Cavin, Anwar Rohillah, Douglas M. Carmean