Abstract: A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data, an intermediate frame buffer that receives the de-mapped physical channel data, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data. The back end processor may include a third stage, including a scaling circuit to scale the encoded transport channel data, a decoder to decode the scaled transport channel data, a CRC checker and an output buffer.

Abstract: A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data, an intermediate frame buffer that receives the de-mapped physical channel data, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data. The back end processor may include a third stage, including a scaling circuit to scale the encoded transport channel data, a decoder to decode the scaled transport channel data, a CRC checker and an output buffer.

Abstract: An apparatus for processing signals in a wireless system includes a first memory module to receive input data from a set of physical channels, a first plurality of sub-modules to process the input data. Each of the first plurality of sub-modules is selected to function based upon data and transmission channel specifications. The apparatus also includes a second memory module to receive processed input data and output intermediate data. Locations of the input data in the second memory is allocated in connection with data and transmission channel specifications. The apparatus also includes a second plurality of sub-modules to process the intermediate data. Each of the second plurality of sub-modules is selected to function based upon data and transmission channel specifications. The apparatus also includes a third memory module to receive and output bit rate processing output.

Abstract: An apparatus for processing signals in a wireless system includes a first memory module to receive input data from a set of physical channels, a first plurality of sub-modules to process the input data. Each of the first plurality of sub-modules is selected to function based upon data and transmission channel specifications. The apparatus also includes a second memory module to receive processed input data and output intermediate data. Locations of the input data in the second memory is allocated in connection with data and transmission channel specifications. The apparatus also includes a second plurality of sub-modules to process the intermediate data. Each of the second plurality of sub-modules is selected to function based upon data and transmission channel specifications. The apparatus also includes a third memory module to receive and output bit rate processing output.

Abstract: A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data from the frame buffer, an intermediate frame buffer that receives the de-mapped physical channel data from the first stage, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data.

Abstract: A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data from the frame buffer, an intermediate frame buffer that receives the de-mapped physical channel data from the first stage, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data.

Abstract: A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data from the frame buffer, an intermediate frame buffer that receives the de-mapped physical channel data from the first stage, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data.

Abstract: A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data from the frame buffer, an intermediate frame buffer that receives the de-mapped physical channel data from the first stage, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data.

Abstract: A method of processing received L1 and L2 spread spectrum signals is disclosed. In one embodiment, the method comprises i) locally generating replicas of a known P-code, wherein each of the received signals includes a unique frequency carrier with the known pseudo-random P-code and an unknown code modulated thereon, ii) making the code replicas available at different relative phases, iii) demodulating the received L1 and L2 signals with replicas of the P-code, iv) repetitively and separately integrating the demodulated L1 and L2 signals over time periods related to the unknown code, and v) correlating an integration result for one of the L1 and L2 signals with an integration result for the other of the L1 and L2 signals.

Abstract: An apparatus for processing received spread spectrum signals modulated with a unique pseudo-random code is disclosed. In one embodiment, the apparatus comprises i) a plurality of channel modules each including a correlator, ii) a circuit configured to hierarchically chain a plurality of the channel modules in series, wherein at least one of a code, control signals and carrier signals is passed from one channel module of the chain to the next, and iii) a selector configured to select the at least one of the code, control signals and carrier signals, to be transmitted to the next channel module in the chain with a delay or without a delay.

Abstract: An electronic system for receiving spread spectrum signals, in particular GPS and/or GLONASS signals is described. In particular, the functional specification for the design of an advanced GPS and/or GLONASS receiver (AGGR) is disclosed. The AGGR is preferably fabricated including at least one sub-system implemented as an application specific integrated circuit (ASIC). The present disclosure describes the AGGR functionality and its modes of operation to a detail allowing a future user of the device to understand its features and limitations and to assess its suitability for an envisaged application. A method and an apparatus are described for processing received spread spectrum signals modulated with a unique pseudo-random code including a capability of hierarchically chaining a plurality of channel modules in series, specific forms of delay line units and correlator units which can process CA-code, P-code and Y-code signals.

Abstract: The invention relates to a navigation system receiver comprising at least two antennas, one of which is a "reference" antenna. A multiplexer multiplexes the signals from the antennas, and a first processor situated downstream from the multiplexer delivers at least one navigation parameter on the basis of the signals from the multiplexer. The receiver includes a second processor having an input receiving in continuous manner signals from the reference antenna to deliver at least one reference signal representative of a position parameter of the reference antenna. Processor means process the signals from the multiplexer while taking account of at least one said reference signal.