Abstract: Provided herein are methods for treating a lysosomal transmembrane protein disease or disorder through ex vivo introduction of a nucleic acid molecule into hematopoietic stem and progenitor cells (HSPCs) followed by transplantation of the HSPCs into a subject in need of treatment. Also provided are vectors containing the nucleic acid molecule.

Abstract: Provided herein are methods for treating a lysosomal transmembrane protein disease or disorder through ex vivo introduction of a nucleic acid molecule into hematopoietic stem and progenitor cells (HSPCs) followed by transplantation of the HSPCs into a subject in need of treatment. Also provided are vectors containing the nucleic acid molecule.

Abstract: Provided herein are gene therapy vectors containing a polynucleotide encoding a cardiac-specific promoter operably linked to a polynucleotide encoding Troponin I3, and methods of using such vectors for preventing, mitigating, ameliorating, reducing, inhibiting, eliminating and/or reversing one or more symptoms of cardiomyopathy.

Abstract: Provided herein are methods for treating a lysosomal transmembrane protein disease or disorder through ex vivo introduction of a nucleic acid molecule into hematopoietic stem and progenitor cells (HSPCs) followed by transplantation of the HSPCs into a subject in need of treatment. Also provided are vectors containing the nucleic acid molecule.

Abstract: The present invention relates to metal-insulator-metal (MIM) capacitors and field effect transistors (FETs) formed on a semiconductor substrate. The FETs are formed in Front End of Line (FEOL) levels below the MIM capacitors which are formed in upper Back End of Line (BEOL) levels. An insulator layer is selectively formed to encapsulate at least a top plate of the MIM capacitor to protect the MIM capacitor from damage due to process steps such as, for example, reactive ion etching. By selective formation of the insulator layer on the MIM capacitor, openings in the inter-level dielectric layers are provided so that hydrogen and/or deuterium diffusion to the FETs can occur.

Abstract: A method for calibrating a software model for a given structure of interest for a variable imposed by an adjacent structure. First determine the spatial extent of the variable imposed by the adjacent structure. Then assign a value to the spatial extent, which varies as a function of distance from the adjacent structure to the given structure. Finally, attach that value to the model of the given structure.

Abstract: A method for calibrating a software model for a given structure of interest for a variable imposed by an adjacent structure. First determine the spatial extent of the variable imposed by the adjacent structure. Then assign a value to the spatial extent, which varies as a function of distance from the adjacent structure to the given structure. Finally, attach that value to the model of the given structure.

Abstract: A method for detecting semiconductor process stress-induced defects. The method comprising: providing a polysilicon-bounded test diode, the diode comprising a diffused first region within an upper portion of a second region of a silicon substrate, the second region of an opposite dopant type from the first region, the first region surrounded by a peripheral dielectric isolation, a peripheral polysilicon gate comprising a polysilicon layer over a dielectric layer and the gate overlapping a peripheral portion of the first region; stressing the diode; and monitoring the stressed diode for spikes in gate current during the stress, determining the frequency distribution of the slope of the forward bias voltage versus the first region current at the pre-selected forward bias voltage and monitoring, after stress, the diode for soft breakdown. A DRAM cell may be substituted for the diode. The use of the diode as an antifuse is also disclosed.

Abstract: A capacitor structure is fabricated by forming a bottom plate, forming a dielectric layer overlaying the bottom plate, and forming a top plate over the dielectric layer. In addition, at least one insulating sidewall spacer that protects the dielectric layer during processing is formed along the perimeter of the top plate and overlaying a portion of the dielectric layer.

Abstract: The present invention relates to metal-insulator-metal (MIM) capacitors and field effect transistors (FETs) formed on a semiconductor substrate. The FETs are formed in Front End of Line (FEOL) levels below the MIM capacitors which are formed in upper Back End of Line (BEOL) levels. An insulator layer is selectively formed to encapsulate at least a top plate of the MIM capacitor to protect the MIM capacitor from damage due to process steps such as, for example, reactive ion etching. By selective formation of the insulator layer on the MIM capacitor, openings in the inter-level dielectric layers are provided so that hydrogen and/or deuterium diffusion to the FETs can occur.

Abstract: The present invention relates to metal-insulator-metal (MIM) capacitors and field effect transistors (FETs) formed on a semiconductor substrate. The FETs are formed in Front End of Line (FEOL) levels below the MIM capacitors which are formed in upper Back End of Line (BEOL) levels. An insulator layer is selectively formed to encapsulate at least a top plate of the MIM capacitor to protect the MIM capacitor from damage due to process steps such as, for example, reactive ion etching. By selective formation of the insulator layer on the MIM capacitor, openings in the inter-level dielectric layers are provided so that hydrogen and/or deuterium diffusion to the FETs can occur.

Abstract: The present invention relates to metal-insulator-metal (MIM) capacitors and field effect transistors (FETs) formed on a semiconductor substrate. The FETs are formed in Front End of Line (FEOL) levels below the MIM capacitors which are formed in upper Back End of Line (BEOL) levels. An insulator layer is selectively formed to encapsulate at least a top plate of the MIM capacitor to protect the MIM capacitor from damage due to process steps such as, for example, reactive ion etching. By selective formation of the insulator layer on the MIM capacitor, openings in the inter-level dielectric layers are provided so that hydrogen and/or deuterium diffusion to the FETs can occur.

Abstract: A method for detecting semiconductor process stress-induced defects. The method comprising: providing a polysilicon-bounded test diode, the diode comprising a diffused first region within an upper portion of a second region of a silicon substrate, the second region of an opposite dopant type from the first region, the first region surrounded by a peripheral dielectric isolation, a peripheral polysilicon gate comprising a polysilicon layer over a dielectric layer and the gate overlapping a peripheral portion of the first region; stressing the diode; and monitoring the stressed diode for spikes in gate current during the stress, determining the frequency distribution of the slope of the forward bias voltage versus the first region current at the pre-selected forward bias voltage and monitoring, after stress, the diode for soft breakdown. A DRAM cell may be substituted for the diode. The use of the diode as an antifuse is also disclosed.

Abstract: A capacitor structure formed on an insulation layer includes a lower electrode formed on a surface of the insulation layer, a dielectric layer formed on a surface of the lower electrode, an upper electrode formed on a surface of the dielectric layer, a first spacer formed on a side portion of the upper electrode, and a second spacer formed on a side portion of the first spacer and a side portion of the lower electrode. This capacitor structure is formed by depositing a metal-insulator-metal capacitor stack on top of a via, masking and etching an upper electrode of the metal-insulator-metal capacitor stack, depositing and etching a first spacer on an edge surface of the upper electrode, defining a lower electrode of the metal-insulator-metal capacitor based on the first spacer, depositing and etching a second spacer on a surface of the first spacer and an edge of the lower electrode, and forming a wiring layer on a surface of the upper electrode and a surface of the second spacer.

Abstract: A semiconductor device having a conduction channel which is electrically modulated. A trench structure is formed within a substrate enclosing a diffusion region. The trench structure isolates the devices formed within the diffusion region from the remaining portion of the substrate. The trench walls are made thin enough so that the width of the channel within a diffusion region may be controlled by applying an electrical potential between a trench wall and the substrate. Transistors formed within the trench structure have a conduction channel width controlled by the applied voltage permitting the gain of the transistor to be matched with the gain of other transistors on the substrate.

Abstract: A method for calibrating a software model for a given structure of interest for a variable imposed by an adjacent structure. First determine the spatial extent of the variable imposed by the adjacent structure. Then assign a value to the spatial extent, which varies as a function of distance from the adjacent structure to the given structure. Finally, attach that value to the model of the given structure.

Abstract: A semiconductor device having a conduction channel which is electrically modulated. A trench structure is formed within a substrate enclosing a diffusion region. The trench structure isolates the devices formed within the diffusion region from the remaining portion of the substrate. The trench walls are made thin enough so that the width of the channel within a diffusion region may be controlled by applying an electrical potential between a trench wall and the substrate. Transistors formed within the trench structure have a conduction channel width controlled by the applied voltage permitting the gain of the transistor to be matched with the gain of other transistors on the substrate.

Abstract: A varactor circuit having an increased tuning range comprises a first varactor in series with a second varactor between first and second terminals. A resistor is connected between the first and second terminals. A tap of the resistor is connected to a junction of the first and second varactors. This circuit effectively doubles tuning range compared to a single varactor.

Abstract: A method for detecting semiconductor process stress-induced defects. The method comprising: providing a polysilicon-bounded test diode, the diode comprising a diffused first region within an upper portion of a second region of a silicon substrate, the second region of an opposite dopant type from the first region, the first region surrounded by a peripheral dielectric isolation, a peripheral polysilicon gate comprising a polysilicon layer over a dielectric layer and the gate overlapping a peripheral portion of the first region; stressing the diode; and monitoring the stressed diode for spikes in gate current during the stress, determining the frequency distribution of the slope of the forward bias voltage versus the first region current at the pre-selected forward bias voltage and monitoring, after stress, the diode for soft breakdown. A DRAM cell may be substituted for the diode. The use of the diode as an antifuse is also disclosed.

Abstract: A capacitor structure formed on an insulation layer includes a lower electrode formed on a surface of the insulation layer, a dielectric layer formed on a surface of the lower electrode, an upper electrode formed on a surface of the dielectric layer, a first spacer formed on a side portion of the upper electrode, and a second spacer formed on a side portion of the first spacer and a side portion of the lower electrode. This capacitor structure is formed by depositing a metal-insulator-metal capacitor stack on top of a via, masking and etching an upper electrode of the metal-insulator-metal capacitor stack, depositing and etching a first spacer on an edge surface of the upper electrode, defining a lower electrode of the metal-insulator-metal capacitor based on the first spacer, depositing and etching a second spacer on a surface of the first spacer and an edge of the lower electrode, and forming a wiring layer on a surface of the upper electrode and a surface of the second spacer.