Abstract: A processor core may include circuitry that fetches a first instruction followed by a second instruction. The first instruction may be configured to cause a first memory request, and the second instruction may be configured to cause a second memory request. The circuitry may determine that the first memory request is a candidate for combination with the second memory request. Responsive to the determination, the circuitry may send an indication, from the processor core via a bus, that the first memory request is a candidate for combination.