Patents by Inventor Eric Andrew Joseph

Eric Andrew Joseph has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8426967
    Abstract: A semiconductor structure configurable for use as a nonvolatile storage element includes a first electrode, an insulating layer formed on at least a portion of an upper surface of the first electrode, and a pillar traversing the insulating layer and being recessed relative to an upper surface of the insulating layer. The pillar includes a heater formed on at least a portion of the upper surface of the first electrode and a collar formed on sidewalls of the insulating layer proximate the heater and on at least a portion of an upper surface of the heater. The structure further includes a PCM layer formed on at least a portion of the upper surface of the insulating layer and substantially filling a volume defined by the upper surface of the heater and at least a portion of an upper surface of the collar. A second electrode is formed on at least a portion of an upper surface of the phase change material layer.
    Type: Grant
    Filed: January 5, 2007
    Date of Patent: April 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Eric Andrew Joseph, Chung Hon Lam, Alejandro Gabriel Schrott
  • Publication number: 20120193715
    Abstract: A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench.
    Type: Application
    Filed: April 9, 2012
    Publication date: August 2, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sebastian Ulrich Engelmann, Nicholas C.M. Fuller, Eric Andrew Joseph, Isaac Lauer, Ryan M. Martin, James Vichiconti, Ying Zhang
  • Publication number: 20120193680
    Abstract: A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench.
    Type: Application
    Filed: April 9, 2012
    Publication date: August 2, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sebastian Ulrich Engelmann, Nicholas C.M. Fuller, Eric Andrew Joseph, Isaac Lauer, Ryan M. Martin, James Vichiconti, Ying Zhang
  • Patent number: 8232171
    Abstract: A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench.
    Type: Grant
    Filed: September 17, 2009
    Date of Patent: July 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: Sebastian Ulrich Engelmann, Nicholas C. M. Fuller, Eric Andrew Joseph, Isaac Lauer, Ryan M. Martin, James Vichiconti, Ying Zhang
  • Patent number: 8138028
    Abstract: A method for manufacturing a mushroom-cell type phase change memory is based upon manufacturing a pillar of bottom electrode material upon a substrate including an array of conductive contacts in electrical communication with access circuitry. A layer of electrode material is deposited making reliable electrical contact with the array of conductive contacts. Electrode material is etched to form a pattern of electrode pillars on corresponding conductive contacts. Next, a dielectric material is deposited over the pattern and planarized to provide an electrode surface exposing top surfaces of the electrode pillars. Next, a layer of programmable resistive material, such as a chalcogenide or other phase change material, is deposited, followed by deposition of a layer of a top electrode material. A device including bottom electrode pillars with larger bottom surfaces than top surfaces is described.
    Type: Grant
    Filed: June 18, 2007
    Date of Patent: March 20, 2012
    Assignees: Macronix International Co., Ltd, International Business Machines Corporation, Qimonda North America Corp.
    Inventors: Hsiang Lan Lung, Chieh Fang Chen, Yi Chou Chen, Shih Hung Chen, Chung Hon Lam, Eric Andrew Joseph, Alejandro Gabriel Schrott, Matthew J. Breitwisch, Geoffrey William Burr, Thomas D. Happ, Jan Boris Philipp
  • Patent number: 8115186
    Abstract: A memory cell is fabricated by forming a dielectric layer and patterning a hole in the dielectric layer. Patterning the hole is accomplished at least in part by contacting the dielectric layer with a catalytic material in the presence of a reactant under conditions effective to remove those areas of the dielectric layer in contact with the catalytic material. A phase change feature is then formed in contact with the dielectric layer such that a portion of the phase change feature at least partially fills the hole in the dielectric layer. At least a portion of the patterned dielectric layer remains in the ultimate memory cell.
    Type: Grant
    Filed: July 7, 2009
    Date of Patent: February 14, 2012
    Assignee: International Business Machines Corporation
    Inventors: Matthew J. Breitwisch, Roger W. Cheek, Eric Andrew Joseph, Chung Hon Lam, Hsiang-Lan Lung, Alejandro Gabriel Schrott
  • Publication number: 20110062494
    Abstract: A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench.
    Type: Application
    Filed: September 17, 2009
    Publication date: March 17, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sebastian Ulrich Engelmann, Nicholas C.M. Fuller, Eric Andrew Joseph, Isaac Lauer, Ryan M. Martin, James Vichiconti, Ying Zhang
  • Publication number: 20090294748
    Abstract: A memory cell is fabricated by forming a dielectric layer and patterning a hole in the dielectric layer. Patterning the hole is accomplished at least in part by contacting the dielectric layer with a catalytic material in the presence of a reactant under conditions effective to remove those areas of the dielectric layer in contact with the catalytic material. A phase change feature is then formed in contact with the dielectric layer such that a portion of the phase change feature at least partially fills the hole in the dielectric layer. At least a portion of the patterned dielectric layer remains in the ultimate memory cell.
    Type: Application
    Filed: July 7, 2009
    Publication date: December 3, 2009
    Applicant: International Business Machines Corporation
    Inventors: Matthew J. Breitwisch, Roger W. Cheek, Eric Andrew Joseph, Chung Hon Lam, Hsiang-Lan Lung, Alejandro Gabriel Schrott
  • Publication number: 20080265234
    Abstract: A memory cell is fabricated by forming a dielectric layer and patterning a hole in the dielectric layer. Patterning the hole is accomplished at least in part by contacting the dielectric layer with a catalytic material in the presence of a reactant under conditions effective to remove those areas of the dielectric layer in contact with the catalytic material. A phase change feature is then formed in contact with the dielectric layer such that a portion of the phase change feature at least partially fills the hole in the dielectric layer. At least a portion of the patterned dielectric layer remains in the ultimate memory cell.
    Type: Application
    Filed: April 30, 2007
    Publication date: October 30, 2008
    Inventors: Matthew J. Breitwisch, Roger W. Cheek, Eric Andrew Joseph, Chung Hon Lam, Hsiang-Lan Lung, Alejandro Gabriel Schrott
  • Publication number: 20080191187
    Abstract: A method for manufacturing a mushroom-cell type phase change memory is based upon manufacturing a pillar of bottom electrode material upon a substrate including an array of conductive contacts in electrical communication with access circuitry. A layer of electrode material is deposited making reliable electrical contact with the array of conductive contacts. Electrode material is etched to form a pattern of electrode pillars on corresponding conductive contacts. Next, a dielectric material is deposited over the pattern and planarized to provide an electrode surface exposing top surfaces of the electrode pillars. Next, a layer of programmable resistive material, such as a chalcogenide or other phase change material, is deposited, followed by deposition of a layer of a top electrode material. A device including bottom electrode pillars with larger bottom surfaces than top surfaces is described.
    Type: Application
    Filed: June 18, 2007
    Publication date: August 14, 2008
    Applicants: MACRONIX INTERNATIONAL CO., LTD., INTERNATIONAL BUSINESS MACHINES CORPORATION, QIMONDA NORTH AMERICA CORP.
    Inventors: HSIANG LAN LUNG, CHIEH-FANG CHEN, YI-CHOU CHEN, SHIH HUNG CHEN, CHUNG HON LAM, ERIC ANDREW JOSEPH, ALEJANDRO GABRIEL SCHROTT, MATTHEW J. BREITWISCH, GEOFFREY WILLIAM BURR, THOMAS D. HAPP, JAN BORIS PHILIPP
  • Publication number: 20080164452
    Abstract: A semiconductor structure configurable for use as a nonvolatile storage element includes a first electrode, an insulating layer formed on at least a portion of an upper surface of the first electrode, and a pillar traversing the insulating layer and being recessed relative to an upper surface of the insulating layer. The pillar includes a heater formed on at least a portion of the upper surface of the first electrode and a collar formed on sidewalls of the insulating layer proximate the heater and on at least a portion of an upper surface of the heater. The structure further includes a PCM layer formed on at least a portion of the upper surface of the insulating layer and substantially filling a volume defined by the upper surface of the heater and at least a portion of an upper surface of the collar. A second electrode is formed on at least a portion of an upper surface of the phase change material layer.
    Type: Application
    Filed: January 5, 2007
    Publication date: July 10, 2008
    Inventors: Eric Andrew Joseph, Chung Hon Lam, Alejandro Gabriel Schrott