Abstract: A method and apparatus for detecting and correcting digit errors of arithmetic results and signed data represented in a redundant residue number system (RRNS) and further represented using a non-systematic method of complements suitable for processing by a complement based digital arithmetic of the full redundant range.

Abstract: A method and apparatus for detecting and correcting digit errors of arithmetic results and signed data represented in a redundant residue number system (RRNS) and further represented using a non-systematic method of complements suitable for processing by a complement based digital arithmetic of the full redundant range

Abstract: Arithmetic circuits and methods that perform efficient matrix multiplication for hardware acceleration of neural networks, machine learning, web search and other applications are disclosed herein. Various arrays of multiplier-accumulators may be coupled to form a matrix multiplier which processes data using high precision, fixed point residue number arithmetic.

Abstract: Arithmetic circuits and methods that perform efficient conversion of fractional RNS representations to fractional binary representations is disclosed herein.

Abstract: Arithmetic circuits and methods that perform efficient matrix multiplication for hardware acceleration of neural networks, machine learning, web search and other applications are disclosed herein. Various arrays of multiplier-accumulators may be coupled to form a matrix multiplier which processes data using high precision, fixed point residue number arithmetic.

Abstract: Arithmetic circuits and methods that perform efficient conversion of fractional RNS representations to fractional binary representations is disclosed herein.

Abstract: Arithmetic circuits and methods that perform efficient matrix multiplication for hardware acceleration of neural networks, machine learning, web search and other applications are disclosed herein. Various arrays of multiplier-accumulators may be coupled to form a matrix multiplier which processes data using high precision, fixed point residue number arithmetic.

Abstract: Arithmetic circuits and methods that perform efficient matrix multiplication for hardware acceleration of neural networks, machine learning, web search and other applications are disclosed herein. Various arrays of multiplier-accumulators may be coupled to form a matrix multiplier which processes data using high precision, fixed point residue number arithmetic.

Abstract: Arithmetic circuits and methods that perform efficient matrix multiplication for hardware acceleration of neural networks, machine learning, web search and other applications are disclosed herein. Various arrays of multiplier-accumulators may be coupled to form a matrix multiplier which processes data using high precision, fixed point residue number arithmetic.

Abstract: A table bonusing system presents a bonus game with a jackpot and one or more ancillary awards to players of a base game at a gaming table. The table bonusing system comprises a controller in communication with one or more gaming tables. Qualifying wagers placed during the base game increment the jackpot and cause a card to be drawn from the bonus game's deck of cards. When the drawn card is of a randomly selected suit, the card is included in a set of placed cards. The jackpot is awarded when the set of placed cards forms a winning outcome. The controller presents its bonus game to players via a display at the gaming tables.

Abstract: Methods and systems for residue number system based ALUs, processors, and other hardware provide the full range of arithmetic operations while taking advantage of the benefits of the residue numbers in certain operations.

Abstract: Methods and systems for residue number system based ALUs, processors, and other hardware provide the full range of arithmetic operations while taking advantage of the benefits of the residue numbers in certain operations. In one or more embodiments, an RNS ALU or processor comprises a plurality of digit slices configured to perform modular arithmetic functions. Operation of the digit slices may be controlled by a controller. Residue numbers may be converted to and from fixed or mixed radix number systems for internal use and for use in various computing systems.

Abstract: Methods and systems for conversion of binary data to residue data, and for conversion of residue data to binary data, allow fully extensible operation with related methods and systems for residue number based ALUs, processors and other hardware. In one or more embodiments, a residue to binary data converter apparatus comprises a mixed radix to fixed radix conversion apparatus. In one or more embodiments, a mixed radix converter apparatus assists internal processing of a related residue number based ALU, processor or other hardware.

Abstract: A mystery jackpot system having an restricted payout scheme allows a mystery jackpot to be incremented by player wagers in a rapid fashion while providing incentives to players to make larger wagers. The mystery jackpot system may have a primary jackpot pool and a secondary jackpot pool. The primary jackpot pool may be funded by eligible wagers, while the secondary jackpot pool may be funded by smaller ineligible wagers. The amount or value of the primary jackpot pool may be used to determine whether the mystery jackpot is active. For example, the mystery jackpot may be active and awardable only if the primary jackpot pool is above a particular amount and below a maximum amount. A player winning the mystery jackpot may be awarded both the primary and secondary jackpot pools. Only players making eligible wagers may win the mystery jackpot.

Abstract: Methods and systems for residue number system based ALUs, processors, and other hardware provide the full range of arithmetic operations while taking advantage of the benefits of the residue numbers in certain operations. In one or more embodiments, an RNS ALU or processor comprises a plurality of digit slices configured to perform modular arithmetic functions. Operation of the digit slices may be controlled by a controller. Residue numbers may be converted to and from fixed or mixed radix number systems for internal use and for use in various computing systems.

Abstract: Methods and systems for residue number system based ALUs, processors, and other hardware provide the full range of arithmetic operations while taking advantage of the benefits of the residue numbers in certain operations. In one or more embodiments, an RNS ALU or processor comprises a plurality of digit slices configured to perform modular arithmetic functions. Operation of the digit slices may be controlled by a controller. Residue numbers may be converted to and from fixed or mixed radix number systems for internal use and for use in various computing systems.

Abstract: A random payout system provides self-funding winning symbol combinations that allow various wagering games to be quickly and easily defined. The winning symbol combinations may individually be associated with a funding pool. Symbols from a winning symbol combination may be disabled or not presented when an associated funding pool is negative. The symbols may be activated or presented when the associated funding pool is non-negative. In this manner, the winning symbol combinations are self-funding. Funds for a funding pool may come from various sources including advertising revenue and placed wagers.

Abstract: Methods and systems for residue number system based ALUs, processors, and other hardware provide the full range of arithmetic operations while taking advantage of the benefits of the residue numbers in certain operations.

Abstract: A mystery-bingo jackpot having increased payout opportunities provides a dynamic bonus game where achievement of a secondary winning outcome initiates an award payout without resetting the jackpot's amount. The secondary winning outcome will typically be configured to have a higher likelihood of occurrence as compared to other winning outcomes of the mystery-bingo jackpot. In this way, the mystery-bingo jackpot provides payouts relatively often while preserving the value of the jackpot.

Abstract: Methods and systems for conversion of binary data to residue data, and for conversion of residue data to binary data, allow fully extensible operation with related methods and systems for residue number based ALUs, processors and other hardware. In one or more embodiments, a residue to binary data converter apparatus comprises a mixed radix to fixed radix conversion apparatus. In one or more embodiments, a mixed radix converter apparatus assists internal processing of a related residue number based ALU, processor or other hardware.