Abstract: The invention relates to a method of managing an embedded system comprising at least one original code which is associated with a computer device, at least one embedded code which is associated with the embedded system, and at least one processor which is associated with said embedded system. The invention is characterized in that it comprises a first step involving the creation of at least one autonomous software component, consisting in: analyzing the original code in order to identify the target functions that are called by the original code but not implemented in said code; determining a corresponding function identifier for each of said non-implemented functions; and replacing said non-implemented function calls with at least one switching function PLUG call which is implemented by the embedded code.

Abstract: The invention relates to a method of managing an embedded system comprising at least one original code which is associated with a computer device, at least one embedded code which is associated with the embedded system, and at least one processor which is associated with said embedded system. The invention is characterized in that it comprises a first step involving the creation of at least one autonomous software component, consisting in: analyzing the original code in order to identify the target functions that are called by the original code but not implemented in said code; determining a corresponding function identifier for each of said non-implemented functions; and replacing said non-implemented function calls with at least one switching function PLUG call which is implemented by the embedded code.

Abstract: An apparatus for and method of generating a clock signal having a desired frequency that is derived from a clock source having any arbitrary,frequency. The mechanism of the present invention generates an average rate, very close to the optimal rate desired, by ‘swallowing’ or absorbing clock cycles of the available frequency source. Precise timing is achieved by adding correcting time intervals, which are based on counting pulses from the higher rate clock source. The clock frequency generator comprises a standby mode state machine and a jitter calculation processor. Timing calculations are performed by the jitter calculation processor and the standby mode state machine functions to generate the desired standby mode clock frequency. The state machine utilizes counters to track the number of cycles of the available clock and the number of generated cycles of the standby clock.

Abstract: Device for estimating the frequency offset in a signal received by a differential demodulator of a mobile-telephone set, intended for implementing the method according to one of claims 1 to 3, characterized in that it has means (1) for calculating an error signal &egr; on the basis of the phase &phgr; of the output signal of the demodulator and the ideal phase &phgr;o of this signal, means (4) for establishing the absolute value (ABS) of the error signal &egr;, means (2, 5, 7) for calculating an estimate of the average of the error signal &egr; calculated over a certain number of samples, from which estimate nFO-RAW bits are taken, means (3, 6, 8) for calculating an estimate of the average of the absolute value of the error signal &egr; over a certain number of samples, from which estimate nQ-RAW bits are taken, and means (10) for modelling a frequency-offset function &OHgr;(FO-RAW, Q-RAW) on the basis of the said estimates.

Abstract: Device for recovering synchronization on a signal transmitted to a mobile-telephone receiver, including phase-estimator means (47, 49) for the absolute value (ABS) and the sign (SIGN) of the transmitted signal, estimation processor (64) for processing the output signals of the estimators (47, 49), a sequencer (67), one input of which is connected to the output of the processor (64) and one output of which applies a mode signal to the processor, another output of the sequencer (67) being connected via a sampling-time generator (68) to the sampling-time control inputs of the estimators (47, 49).

Abstract: A circuit is designed with a delay circuit (102) coupled to receive a frequency-modulated data signal (100) at a delay input terminal. The delay circuit produces the data signal (103) after a predetermined delay at a delay output terminal. An exclusive OR circuit (104) has a first input terminal coupled to the delay input terminal and has a second input terminal coupled to the delay output terminal.