Abstract: Memory is divided up during the gathering of histogram data so that a portion of the memory is configured for storing the high counts expected at the minimum and maximum codes/addresses, and at least one other portion is configured for storing the lower counts expected at other codes/addresses. By configuring memory portions in this manner, memory can be more efficiently allocated.

Abstract: Disclosed is a method and apparatus for calibrating a time vernier in an automatic test equipment (ATE) system, the method including generating a data signal and a reference signal whose periods differ by a small amount (dt), using precession of the data signal and reference signal to create accurate delay increments, and creating a trigger signal for Bit Error Rate Test (BERT) counting, the trigger signal having a select frequency such than an integer number (N) of triggers are generated with a precession period (TPREC). Upon occurrence of each trigger, a BERT is initiated for measuring data to determine strobe positions with respect to the data signal.

Abstract: Provided is a test apparatus, a differential signal transmission circuit, and a transmission circuit that transmits signals between an input terminal and an output terminal, comprising a first high frequency signal passing section that blocks a low frequency signal that has a frequency less than a predetermined reference frequency in a signal received from the input terminal, and transmits a high frequency signal that has a frequency greater than or equal to the predetermined reference frequency to the output terminal; an input-side low frequency signal passing section that passes the low frequency signal in the signal from the input terminal and attenuates the high frequency signal; an output-side low frequency signal passing section that transmits to the output terminal the low frequency signal passed by the input-side low frequency signal passing section and attenuates the high frequency signal from the first high frequency signal passing section; and a switching section that switches a connection between

Abstract: Disclosed is a method and apparatus for calibrating a time vernier with an input data signal, a reference signal and a third trigger signal, all of which have pre-defined related frequencies so as to allow for accurate determination of vernier delays and strobe placement in an ATE system.

Abstract: Dividing memory used for storing histogram data into multiple banks is disclosed to allow for phased RMW cycles. Although the same address lines are provided to each bank, address control logic ensures that each successive RMW cycle is handled by a different bank, so that another RMW cycle can be started in one bank while the previous RMW cycle is still being performed in another bank. By staggering or phasing the starts of the RMW cycles in a wraparound fashion, each histogram bin is spread out over multiple banks, but testing can proceed faster than if only a single bank was used. After the histogram data has been captured, the areas of memory in each bank associated with a particular bin can be added together to compute the total count for that bin.

Abstract: A method and apparatus for synchronizing digital and analog/mixed signal modules in a test site of an open architecture test system is disclosed. Event triggers from digital modules are routed to an ASYNC module, which selectively distributes them to analog/mixed signal modules. When an event occurs, the trigger may activate an analog/mixed signal module to perform a certain operation. The ASYNC module may also receive triggers from the analog/mixed signal modules and selectively distribute them back to the digital modules or analog/mixed signal modules. The digital modules can be programmed to wait for an analog/mixed signal module to complete an operation, as indicated by a trigger received from that analog/mixed signal module, before continuing. Because embodiments of the present invention enable synchronization of digital and analog/mixed signal modules under pattern control, synchronization can be very precise and repeatable as compared to synchronization from a site controller.

Abstract: A loopback module is disclosed in which N differential High Speed Serial (HSS) digital data input channels are received and sent to a serial to parallel converter, whose output is M-bit wide parallel data. By doing so, the effective data rate is divided down by M to 1/M “fabric” speeds. If the channels contain an embedded clock, the clock is extracted. The parallel data is then sent to a non-blocking crossbar switch, which is able to route any of the N M-bit parallel data inputs to any of Q parallel data outputs by effectively utilizing one multiplexer for each parallel output. Each parallel data output of the crossbar is sent to a parallel to serial converter, whose output is a high speed serial output. Each high speed serial output is fed into a jitter generator circuit, and then to an output driver.

Abstract: The present invention is directed to the use of a DDS to generate a high purity reference signal with high frequency resolution by switching a frequency tuning word (FTW) between particular values for particular time durations to produce two or more closely spaced frequencies that appear at the DDS output as a single frequency. Given a DDS switching between F1 and F2 such that F1 is present for time T1 and F2 is present for time T2, with the total period of the repeating pattern being T=T1+T2, in order for the output of the DDS to produce a single high-purity frequency that is the time-weighted average of the alternating frequencies, the condition |F1?F2|<<?/T must be satisfied. The time-weighted average frequency Favg=(T1·F1+T2·F2)/(T+T2). By an appropriate choice of T1 and T2, Favg can be set to any frequency between these two frequencies.

Abstract: Dividing memory used for storing histogram data into multiple banks is disclosed to allow for phased RMW cycles. Although the same address lines are provided to each bank, address control logic ensures that each successive RMW cycle is handled by a different bank, so that another RMW cycle can be started in one bank while the previous RMW cycle is still being performed in another bank. By staggering or phasing the starts of the RMW cycles in a wraparound fashion, each histogram bin is spread out over multiple banks, but testing can proceed faster than if only a single bank was used. After the histogram data has been captured, the areas of memory in each bank associated with a particular bin can be added together to compute the total count for that bin.

Abstract: Memory is divided up during the gathering of histogram data so that a portion of the memory is configured for storing the high counts expected at the minimum and maximum codes/addresses, and at least one other portion is configured for storing the lower counts expected at other codes/addresses. By configuring memory portions in this manner, memory can be more efficiently allocated.

Abstract: A carrier module that is able to adapt non-standard instrument cards to the architecture of a test system is disclosed. Instrument cards based on non-standard architectures may be combined on a single carrier module. The carrier module is then plugged into the test head of the test system. The carrier module provides circuitry, contained on a plug-in sub-module called an Application Interface Adapter (AIA), to interface between the instrument cards and the test head interface connector. Additionally, the AIA may also provide access from the instrument cards to ATE system calibration circuitry. The carrier module uses the standard data bus of the test system for housekeeping and control functions. A second bus provides the bus for the non-standard instrument cards. Software drivers provided with the instrument cards are encapsulated with an appropriate wrapper so that the cards run seamlessly in the software environment of the test system.

Abstract: A carrier module that is able to adapt non-standard instrument cards to the architecture of a test system is disclosed. Instrument cards based on non-standard architectures may be combined on a single carrier module. The carrier module is then plugged into the test head of the test system. The carrier module provides circuitry, contained on a plug-in sub-module called an Application Interface Adapter (AIA), to interface between the instrument cards and the test head interface connector. Additionally, the AIA may also provide access from the instrument cards to ATE system calibration circuitry. The carrier module uses the standard data bus of the test system for housekeeping and control functions. A second bus provides the bus for the non-standard instrument cards. Software drivers provided with the instrument cards are encapsulated with an appropriate wrapper so that the cards run seamlessly in the software environment of the test system.

Abstract: A carrier module that is able to adapt non-standard instrument cards to the architecture of a test system is disclosed. Instrument cards based on non-standard architectures may be combined on a single carrier module. The carrier module is then plugged into the test head of the test system. The carrier module provides circuitry, contained on a plug-in sub-module called an Application Interface Adapter (AIA), to interface between the instrument cards and the test head interface connector. Additionally, the AIA may also provide access from the instrument cards to ATE system calibration circuitry. The carrier module uses the standard data bus of the test system for housekeeping and control functions. A second bus provides the bus for the non-standard instrument cards. Software drivers provided with the instrument cards are encapsulated with an appropriate wrapper so that the cards run seamlessly in the software environment of the test system.

Abstract: A loopback module is disclosed in which N differential High Speed Serial (HSS) digital data input channels are received and sent to a serial to parallel converter, whose output is M-bit wide parallel data. By doing so, the effective data rate is divided down by M to 1/M “fabric” speeds. If the channels contain an embedded clock, the clock is extracted. The parallel data is then sent to a non-blocking crossbar switch, which is able to route any of the N M-bit parallel data inputs to any of Q parallel data outputs by effectively utilizing one multiplexer for each parallel output. Each parallel data output of the crossbar is sent to a parallel to serial converter, whose output is a high speed serial output. Each high speed serial output is fed into a jitter generator circuit, and then to an output driver.