Abstract: An inverter includes a mains system side freewheeling pulse converter and a load-side freewheeling pulse converter, which are electrically connected on the DC side via a DC intermediate circuit. The mains system side and load-side freewheeling pulse converters each include switchable current valves in form of semiconductor switches that are made of silicon carbide with a high blocking voltage. The inverter can operate at higher voltages and frequencies, without affecting the load rating.

Abstract: A hybrid power MOSFET, comprising a MOSFET and a junction FET, the MOSFET and the junction FET being electrically connected in series is disclosed. In accordance with the present invention, the hybrid power MOSFET is provided with a device for reducing the change in the gate voltage of the junction FET. Thus, a hybrid power MOSFET is obtained in which high over-voltages no longer arise and whose EMC response is much improved.

Abstract: A method and an apparatus for turning off a cascode circuit comprising a series circuit formed by a low-blocking-capability and high-blocking-capability semiconductor switch, are described. When a turn-off command arrives, the gate voltage of the low-blocking-capability semiconductor switch is controlled in such a way that its drain voltage is held constant in the active range of the low-blocking-capability semiconductor switch. Consequently, an impermissible overvoltage at high potential of the cascode circuit at low potential is detected and actively limited.

Abstract: An inverter includes a mains system side freewheeling pulse converter and a load-side freewheeling pulse converter, which are electrically connected on the DC side via a DC intermediate circuit. The mains system side and load-side freewheeling pulse converters each include switchable current valves in form of semiconductor switches that are made of silicon carbide with a high blocking voltage. The inverter can operate at higher voltages and frequencies, without affecting the load rating.

Abstract: A hybrid power MOSFET having a low blocking-capability MOSFET and a high blocking-capability junction FET is disclosed. In accordance with the present invention, this cascode circuit has at least two high blocking-capability junction FETs which are electrically connected in parallel and whose gate connections are respectively electrically conductively connected to the source connection of the low blocking-capability MOSFET by means of a connecting line. Thus, a hybrid power MOSFET for a high current-carrying capacity is obtained whose design technology has been considerably simplified on account of the use of only one control line and n+1 chips.

Abstract: A hybrid power MOSFET, comprising a MOSFET and a junction FET, the MOSFET and the junction FET being electrically connected in series is disclosed. In accordance with the present invention, the hybrid power MOSFET is provided with a device for reducing the change in the gate voltage of the junction FET. Thus, a hybrid power MOSFET is obtained in which high over-voltages no longer arise and whose EMC response is much improved.

Abstract: The invention provides a method by which losses are reduced during the commutation of a free-running, driven power converter valve (T2) of an invertor phase (2) to a current-accepting power converter valve (T1) of said invertor phase (2). The current-accepting power converter valve (T1) is switched on at the beginning of the commutation process and the free-running, driven power converter valve (T2) is rapidly switched off as soon as the value of its drain voltage (UD) is zero.

Abstract: A method and an apparatus for balancing the power loss in at least two electrically parallel-connected cascode circuits, which each have a low-blocking semiconductor switch composed of silicon and a high-blocking-capability semiconductor switch composed of silicon carbide is disclosed. According to the present invention, an output voltage of each low-blocking-capability semiconductor switch is detected, with correction values being established as a function of them, and being superimposed on corresponding control signals for the low-blocking-capability semiconductor switches. An unbalanced current distributor can thus be actively balanced.

Abstract: A hybrid power MOSFET having a low blocking-capability MOSFET and a high blocking-capability junction FET is disclosed. In accordance with the present invention, this cascode circuit has at least two high blocking-capability junction FETs which are electrically connected in parallel and whose gate connections are respectively electrically conductively connected to the source connection of the low blocking-capability MOSFET by means of a connecting line. Thus, a hybrid power MOSFET for a high current-carrying capacity is obtained whose design technology has been considerably simplified on account of the use of only one control line and n+1 chips.

Abstract: The invention relates to a method for reducing losses during the commutation of a free-running, driven power converter valve (T2) of an invertor phase (2) to a current-accepting power converter valve (T1) of said invertor phase (2). According to the invention, the current-accepting power converter valve (T1) is switched on at the beginning of the commutation process and the free-running, driven power converter valve (T2) is rapidly switched off as soon as the value of its drain voltage (UD) is zero. The losses during the commutation process can thus be significantly reduced in a simple manner.

Abstract: A circuit arrangement for precharging the capacitor connected to the output of a line-commutated power converter is described, where an element which limits the charging current of the capacitor to a level which is largely independent of the charging voltage is connected between a direct voltage output of the power converter and the respective terminal of the capacitor.

Abstract: Protecting a gate fully controlled thyristor that is controlled by a drive circuit including a turn-on circuit and a turn-off circuit against overvoltage, is accomplished by monitoring the anode voltage of said gate fully controlled thyristor relative to its cathode voltage. Upon overshoot of the voltage of a predetermined limit, a control signal is generated. This control signal causes the negative voltage source that is connected at the gate of the gate fully controlled thyristor to turn off. The gate fully controlled thyristor is then turned on by means of the turn-on circuit.