Abstract: A voltage controlled oscillator is provided in the form of two ring oscillators 30 and 32. Each oscillator stage 14 includes an invertor 16, a level change accelerating circuit 18 and a level change decelerating circuit 20. The level change accelerating circuit 18 is responsive to an input control signal Vctrl to increase the oscillator frequency by decreasing the propagation delay through the invertor 16. The level change decelerating circuit 20 is responsive to the input control signal Vctrl to decrease the oscillator frequency by increasing the propagation delay through the invertor 16. Pairs of opposing invertors 34, 36, 38, 40 and 42 disposed between output signal lines of corresponding oscillator stages 14 in the two ring oscillators 30 and 32 serve to lock the two ring oscillators in antiphase.

Abstract: An edge triggered latch has an improved transparency window, which is essentially the delay of the N-stack pull-down tree. This minimizes the delay yet guarantees that the circuit will have enough time to evaluate the input data, since the evaluation is limited by the pulse width. This circuit eliminates early mode failure for latches placed in series, without the requirement of delay padding.

Abstract: Switching on a first line, from a first signal level to a second level, tends to induce a change in signal level of a second line. To reduce induced noise, the second line is connected to a power rail for a predetermined time interval, responsive to the switching on the first line. The connecting for the time interval tends to counteract the change induced in the second line by the signal of the first line.

Abstract: Performance is increased within a dynamic multiplexer by removing the foot device and replacing it with a logic gate (such as an OR, NOR, or NAND gate) receiving the select signals and activating the precharge device within the dynamic multiplexer circuit. With such a configuration, crowbar current is still inhibited.

Abstract: One aspect of the invention relates to a method for computer aided optimization of a total cost of an electronic circuit, the total cost being a function of a primary cost and at least one secondary cost, the primary and secondary costs being a function of circuit parameters. In one embodiment, the method comprises the steps of selecting an initial vertice, the vertice being defined by specific values of the circuit parameters; selecting a plurality of additional vertices required to define a region; simulating the circuit to determine the primary costs and the secondary costs associated with the vertices in the region; applying a weighting function to the secondary costs which adjusts the secondary costs relative to the deviation of the secondary costs from a predetermined secondary cost target; aggregating the primary costs and the secondary costs to determine individual total costs associated with the vertices in the region.

Abstract: One aspect of the invention relates to a method for computer aided optimization of a cost of an electronic circuit, the cost being a function of a plurality of circuit parameters.

Abstract: A logic block comprised of several transistors is provided. The logic block has several inputs and an output for communicating the result of its logic operation. A precharge device having a clock input is connected to the output of the logic block. The precharge device periodically allows the output of the logic block to become valid. This is accomplished by holding the output of the logic block at a fixed voltage level when the clock input is at a first voltage level, and when the clock input changes to a second voltage level, the precharge device allows the result of the logic function performed by the logic block to appear at the output of the logic block. Also, a charge redistribution prevention device is connected to at least one of the transistors included in the logic block. The charge redistribution prevention device prevents charge redistribution by applying a voltage to at least one of the transistors in the logic block.

Abstract: A logic block comprised of several transistors is provided. The logic block has several inputs and an output for communicating the result of its logic operation. A precharge device having a clock input is connected to the output of the logic block. The precharge device periodically allows the output of the logic block to become valid. This is accomplished by holding the output of the logic block at a fixed voltage level when the clock input is at a first voltage level, and when the clock input changes to a second voltage level, the precharge device allows the result of the logic function performed by the logic block to appear at the output of the logic block. Also, a charge redistribution prevention device is connected to at least one of the transistors included in the logic block. The charge redistribution prevention device prevents charge redistribution by applying a voltage to at least one of the transistors in the logic block.

Abstract: A high performance dynamic logic compatible transparent latch is provided. The latch comprises a first switchable invertor circuit, a second invertor circuit, and a third switchable invertor circuit. The first invertor, having a data input, a clock input and an output, is enabled by a first phase of an input clock and is disabled by a second phase of the input clock. The second invertor has an input connected to the first invertor output. The third invertor has a clock input, and is enabled by the second phase of the input clock and disabled by the first phase of the input clock, and further has an input connected to the second invertor output and an output connected to the second invertor input.

Abstract: A domino logic circuit includes an evaluation circuit for receiving input signals and performing a logic operation on the input signals, a passgate circuit for controlling the transmission of signals to an output circuit and a feedback latch circuit for holding the output of the evaluation circuit for a predetermined portion of a clock cycle. The output circuit may also include a pair of control transistors to allow the output latching circuit to be turned off during the evaluate portion of the clock cycle thus improving the speed of the domino logic circuit. During the first half of the reset portion of each cycle, the output latching circuit is active and allows the circuit to retain its output state. During the time the passgates are turned off, the evaluate circuit is disconnected and may begin resetting. During the second half of the reset portion of the clocking signal, the passgates open, which allows the output stage to be reset.