Abstract: A circuit is for protecting memory address data. The circuit may include an input data bus configured to receive write data to be written to a memory device, and an address bus configured to receive a corresponding write address. The circuit may also include an output data bus, and an address protection circuit coupled to the input data, address, and output data buses and configured to generate an address protection value based on the corresponding write address, and generate modified write data, on the output data bus. The modified write data includes the write data and the address protection value. The output data bus may have a width greater than a width of the input data bus.

Abstract: An electronic device can be used for synchronizing tasks of an appliance that includes a memory access controller having inputs associated with priority levels. The device includes control circuits configured for receiving signals from events and delivering in response signals for activation of tasks. A configurable interface for external events designed to receive first event signals from at least one circuit of the appliance and to route some of them to the corresponding control circuits as a function of a first law of correspondence. A configurable interface for internal events designed to receive second event signals corresponding to the signals for activation of tasks and to route some of them to the control circuits as a function of a second law of correspondence.

Abstract: A circuit is for protecting memory address data. The circuit may include an input data bus configured to receive write data to be written to a memory device, and an address bus configured to receive a corresponding write address. The circuit may also include an output data bus, and an address protection circuit coupled to the input data, address, and output data buses and configured to generate an address protection value based on the corresponding write address, and generate modified write data, on the output data bus. The modified write data includes the write data and the address protection value. The output data bus may have a width greater than a width of the input data bus.

Abstract: An electronic device can be used for synchronizing tasks of an appliance that includes a memory access controller having inputs associated with priority levels. The device includes control circuits configured for receiving signals from events and delivering in response signals for activation of tasks. A configurable interface for external events designed to receive first event signals from at least one circuit of the appliance and to route some of them to the corresponding control circuits as a function of a first law of correspondence. A configurable interface for internal events designed to receive second event signals corresponding to the signals for activation of tasks and to route some of them to the control circuits as a function of a second law of correspondence.

Abstract: An input and/or output pad is dedicated to an integrated circuit comprising a core with input and/or output pins. This pad comprises a pad cell comprising a pad block connected to an input buffer and/or an output buffer and arranged to be connected to one of the core input and/or output pins. The pad also comprises a pad logic module comprising a first and/or a second boundary scan cell, connected to the pad block through the input buffer and/or output buffer and arranged to feed input signals to and/or deliver output signals from the pad block, and control means connected to the first and/or second boundary scan cell(s) and adapted to receive control signals for controlling access to the first and/or second boundary scan cell(s) and feeding the first boundary scan cell with the input signals and/or outputting the output signals delivered by the first boundary scan cell.

Abstract: An interface device (D) is dedicated to debugging and/or tracing in a computer system (CS) comprising at least one master (M1, M2, M3) working with at least one slave (SLj) adapted to be readable and writable at chosen addresses, each master being adapted to execute tasks and to deliver slave addresses for reading and/or writing purposes. This interface device (D) comprises i) a group of first FIFO memories (SMi) each assigned to one master for storing data representative of the tasks it executes, ii) a group of dynamically allocatable second FIFO memories (DFk) linkable to one another and to the first FIFO memories (SFi), and iii) processing means (PM) arranged to compute dynamically the FIFO memory size required by each master at a given time, considering the tasks it is executing, and to allocate dynamically a number of second FIFO memories (DFk) to each master chosen according to the corresponding computed FIFO memory size.

Abstract: An input and/or output pad (P) is dedicated to an integrated circuit comprising a core with input and/or output pins. This pad (P) comprises a pad cell (PC) comprising a pad block (PB) connected to an input buffer (IB1, IB2) and/or an output buffer (OB) and arranged to be connected to one of the core input and/or output pins. The pad (P) also comprises a pad logic module (PLM) comprising a first boundary scan cell (BC1) and/or a second boundary scan cell (BC2), connected to the pad block (PB) through the input buffer (IB1, IB2) and/or output buffer (OB) and arranged to feed input signals to and/or deliver output signals from the pad block (PB), and control means connected to the first (BC1) and/or second (BC2) boundary scan cell(s) and adapted to receive control signals for controlling access to the first and/or second boundary scan cell(s) and feeding the first boundary scan cell (BC1) with the input signals and/or outputting the output signals delivered by the first boundary scan cell (BC 1).

Abstract: An interface device (D) is dedicated to debugging and/or tracing in a computer system (CS) comprising at least one master (M1, M2, M3) working with at least one slave (SLj) adapted to be readable and writable at chosen addresses, each master being adapted to execute tasks and to deliver slave addresses for reading and/or writing purposes. This interface device (D) comprises i) a group of first FIFO memories (SMi) each assigned to one master for storing data representative of the tasks it executes, ii) a group of dynamically allocatable second FIFO memories (DFk) linkable to one another and to the first FIFO memories (SFi), and iii) processing means (PM) arranged to compute dynamically the FIFO memory size required by each master at a given time, considering the tasks it is executing, and to allocate dynamically a number of second FIFO memories (DFk) to each master chosen according to the corresponding computed FIFO memory size.

Abstract: An apparatus, program product and method are provided for use in automating the design of a custom DSP integrated circuit from a preexisting DSP core block and one or more additional circuit blocks interfaced with the DSP core block. An input display is displayed to a user, and is utilized to receive user input from the user for use in automatically building a custom DSP integrated circuit. The input display includes at least one selection input component for use in selecting at least one optional circuit block for inclusion in the custom DSP integrated circuit, and at least one configuration input component for use in customizing a customizable circuit block to be included in the custom DSP integrated circuit. The user input received from the user through the input display selects the optional circuit block and customizes the customizable circuit block.

Abstract: An improved Integrated Circuit (IC) device is delineated comprising, in combination, an IC including an embedded Digital Signal Processor (DSP), an embedded Random Access Memory (RAM), an embedded Read Only Memory (ROM) having at least one portion thereof which is flawed and embedded patching circuitry having as inputs the current DSP program address and at least one break address wherein each break address corresponds to a separate flawed portion of the embedded ROM. The patching circuitry supplies data stored in flawless portions of the ROM to the DSP until the current DSP program address matches a break address indicating that the next portion of the embedded ROM is flawed. In place of the data stored in the flawed portion of the embedded ROM, the patching circuitry supplies corrected data stored in the embedded RAM to the DSP, and after this corrected data is supplied, data transfer to the DSP from the remaining unflawed portions of the embedded ROM is resumed.