Abstract: Described are methods for forming multi-component conductive structures for semiconductor devices. The multi-component conductive structures can include a common metal, present in different percentages between the two components of the conductive structures. As described example, multiple components can include multiple ruthenium materials having different percentages of ruthenium. In some applications, at least a portion of one of the ruthenium material components will be sacrificial, and removed in subsequent processing.

Abstract: Some embodiments disclose a gate stack having a gate (e.g., polysilicon (poly) material) horizontally between shallow trench isolations (STIs), a tungsten silicide (WSix) material over the gate and the STIs, and a tungsten silicon nitride (WSiN) material on a top surface of the WSix material. Some embodiments disclose a gate stack having a gate between STIs, a first WSix material over the gate and the STIs, a WSiN interlayer material on a top surface of the first WSix material, and a second WSix material on a top surface of the WSiN interlayer material. Additional embodiments are disclosed.

Abstract: Described are methods for forming multi-component conductive structures for semiconductor devices. The multi-component conductive structures can include a common metal, present in different percentages between the two components of the conductive structures. As described example, multiple components can include multiple ruthenium materials having different percentages of ruthenium. In some applications, at least a portion of one of the ruthenium material components will be sacrificial, and removed in subsequent processing.

Abstract: Described are methods for forming multi-component conductive structures for semiconductor devices. The multi-component conductive structures can include a common metal, present in different percentages between the two components of the conductive structures. As described example, multiple components can include multiple ruthenium materials having different percentages of ruthenium. In some applications, at least a portion of one of the ruthenium material components will be sacrificial, and removed in subsequent processing.

Abstract: Some embodiments disclose a gate stack having a gate (e.g., polysilicon (poly) material) horizontally between shallow trench isolations (STIs), a tungsten silicide (WSix) material over the gate and the STIs, and a tungsten silicon nitride (WSiN) material on a top surface of the WSix material. Some embodiments disclose a gate stack having a gate between STIs, a first WSix material over the gate and the STIs, a WSiN interlayer material on a top surface of the first WSix material, and a second WSix material on a top surface of the WSiN interlayer material. Additional embodiments are disclosed.

Abstract: Described are methods for forming multi-component conductive structures for semiconductor devices. The multi-component conductive structures can include a common metal, present in different percentages between the two components of the conductive structures. As described example, multiple components can include multiple ruthenium materials having different percentages of ruthenium. In some applications, at least a portion of one of the ruthenium material components will be sacrificial, and removed in subsequent processing.

Abstract: Some embodiments disclose a gate stack having a gate (e.g., polysilicon (poly) material) horizontally between shallow trench isolations (STIs), a tungsten silicide (WSix) material over the gate and the STIs, and a tungsten silicon nitride (WSiN) material on a top surface of the WSix material. Some embodiments disclose a gate stack having a gate between STIs, a first WSix material over the gate and the STIs, a WSiN interlayer material on a top surface of the first WSix material, and a second WSix material on a top surface of the WSiN interlayer material. Additional embodiments are disclosed.

Abstract: Some embodiments disclose a gate stack having a gate (e.g., polysilicon (poly) material) horizontally between shallow trench isolations (STIs), a tungsten silicide (WSix) material over the gate and the STIs, and a tungsten silicon nitride (WSiN) material on a top surface of the WSix material. Some embodiments disclose a gate stack having a gate between STIs, a first WSix material over the gate and the STIs, a WSiN interlayer material on a top surface of the first WSix material, and a second WSix material on a top surface of the WSiN interlayer material. Additional embodiments are disclosed.

Abstract: Methods of forming multi-tiered semiconductor devices are described, along with apparatuses that include them. In one such method, a silicide is formed in a tier of silicon, the silicide is removed, and a device is formed at least partially in a void that was occupied by the silicide. One such apparatus includes a tier of silicon with a void between tiers of dielectric material. Residual silicide is on the tier of silicon and/or on the tiers of dielectric material and a device is formed at least partially in the void. Additional embodiments are also described.

Abstract: Methods of forming multi-tiered semiconductor devices are described, along with apparatuses that include them. In one such method, a silicide is formed in a tier of silicon, the silicide is removed, and a device is formed at least partially in a void that was occupied by the silicide. One such apparatus includes a tier of silicon with a void between tiers of dielectric material. Residual silicide is on the tier of silicon and/or on the tiers of dielectric material and a device is formed at least partially in the void. Additional embodiments are also described.

Abstract: Methods of forming multi-tiered semiconductor devices are described, along with apparatuses that include them. In one such method, a silicide is formed in a tier of silicon, the silicide is removed, and a device is formed at least partially in a void that was occupied by the silicide. One such apparatus includes a tier of silicon with a void between tiers of dielectric material. Residual silicide is on the tier of silicon and/or on the tiers of dielectric material and a device is formed at least partially in the void. Additional embodiments are also described.

Abstract: A 3-D stacked semiconductor device is formed by forming a trench is formed through a top surface in a dielectric layer to expose the crystalline silicon layer having a (100) crystal plane, such that the trench walls are parallel to a <100> direction. Epitaxial silicon is grown between the trench walls to a level that is below the top surface of the dielectric layer. Epitaxial silicon is laterally grown using the top portion of the epitaxially grown silicon as a seed to form a laterally grown epitaxial layer having a (100) crystal plane on the dielectric layer.

Abstract: The present invention is generally directed to a method of forming a pseudo SOI substrate and semiconductor devices. In one illustrative embodiment, the method comprises forming a plurality of trenches in a semiconducting substrate comprised of silicon, each of the trenches having a depth, forming a layer of insulating material within each of the plurality of trenches, the layer of insulating material having a thickness that is less than the depth of the trenches, and performing an anneal process on the substrate in a hydrogen environment to cause the silicon substrate material to merge above the layer of insulating material within the plurality of trenches to thereby define a pseudo SOI substrate.

Abstract: The present invention is generally directed to a method of forming a pseudo SOI substrate and semiconductor devices. In one illustrative embodiment, the method comprises forming a plurality of trenches in a semiconducting substrate comprised of silicon, each of the trenches having a depth, forming a layer of insulating material within each of the plurality of trenches, the layer of insulating material having a thickness that is less than the depth of the trenches, and performing an anneal process on the substrate in a hydrogen environment to cause the silicon substrate material to merge above the layer of insulating material within the plurality of trenches to thereby define a pseudo SOI substrate.

Abstract: The present invention is generally directed to a method of forming a pseudo SOI substrate and semiconductor devices. In one illustrative embodiment, the method comprises forming a plurality of trenches in a semiconducting substrate comprised of silicon, each of the trenches having a depth, forming a layer of insulating material within each of the plurality of trenches, the layer of insulating material having a thickness that is less than the depth of the trenches, and performing an anneal process on the substrate in a hydrogen environment to cause the silicon substrate material to merge above the layer of insulating material within the plurality of trenches to thereby define a pseudo SOI substrate.

Abstract: The invention includes semiconductor processing methods in which openings are formed to extend into a semiconductor substrate, and the substrate is then annealed around the openings to form cavities. The substrate is etched to expose the cavities, and the cavities are substantially filled with insulative material. The semiconductor substrate having the filled cavities therein can be utilized as a semiconductor-on-insulator-type structure, and transistor devices can be formed to be supported by the semiconductor material and to be over the cavities. In some aspects, the transistor devices have channel regions over the filled cavities, and in other aspects the transistor devices have source/drain regions over the filled cavities. The transistor devices can be incorporated into dynamic random access memory, and can be utilized in electronic systems.

Abstract: The invention includes semiconductor processing methods in which openings are formed to extend into a semiconductor substrate, and the substrate is then annealed around the openings to form cavities. The substrate is etched to expose the cavities, and the cavities are substantially filled with insulative material. The semiconductor substrate having the filled cavities therein can be utilized as a semiconductor-on-insulator-type structure, and transistor devices can be formed to be supported by the semiconductor material and to be over the cavities. In some aspects, the transistor devices have channel regions over the filled cavities, and in other aspects the transistor devices have source/drain regions over the filled cavities. The transistor devices can be incorporated into dynamic random access memory, and can be utilized in electronic systems.

Abstract: The invention includes methods of forming epitaxial silicon-comprising material and methods of forming vertical transistors. In one implementation, a method of forming epitaxial silicon-comprising material includes providing a substrate comprising monocrystalline material. A first portion of the monocrystalline material is outwardly exposed while a second portion of the monocrystalline material is masked. A first silicon-comprising layer is epitaxially grown from the exposed monocrystalline material of the first portion and not from the monocrystalline material of the masked second portion. After growing the first silicon-comprising layer, the second portion of the monocrystalline material is unmasked. A second silicon-comprising layer is then epitaxially grown from the first silicon-comprising layer and from the unmasked monocrystalline material of the second portion. Other aspects and implementations are contemplated.

Abstract: In one implementation, a substrate susceptor for receiving a semiconductor substrate for selective epitaxial silicon-comprising depositing thereon, where the depositing comprises measuring emissivity of the susceptor from at least one susceptor location in a non-contacting manner, includes a body having a front substrate receiving side, a back side, and a peripheral edge. At least one susceptor location from which emissivity is to be measured is received on at least one of the front substrate receiving side, the back side, and the edge. Such at least one susceptor location comprises an outermost surface comprising a material upon which selective epitaxial silicon will not deposit upon during selective epitaxial silicon depositing on a semiconductor substrate received by the susceptor for at least an initial thickness of epitaxial silicon depositing on said substrate. Other aspects and implementations are contemplated.

Abstract: The invention includes deposition apparatuses configured to monitor the temperature of a semiconductor wafer substrate by utilizing conduits which channel radiation from the substrate to a detector/signal processor system. In particular aspects, the temperature of the substrate can be measured while the substrate is spinning within a reaction chamber. The invention also includes deposition apparatuses in which flow of mixed gases is controlled by mass flow controllers provided downstream of the location where the gases are mixed and/or where flow of gases is measured with mass flow measurement devices provided downstream of the location where the gases are mixed. Additionally, the invention encompasses deposition apparatuses in which mass flow controllers and/or mass flow measurement devices are provided upstream of a header which splits a source gas into multiple paths directed toward multiple different reaction chambers.