Patents by Inventor Eric Booth
Eric Booth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8018261Abstract: Closed-loop duty-cycle correctors (DCCs), clock generators, memory devices, systems, and methods for generating an output clock signal having a particular duty cycle are provided, such as clock generators configured to generate an output clock signal synchronized with a received input clock signal having a predetermined duty cycle. Embodiments of clock generators include closed-loop duty cycle correctors that receive an already-controlled and corrected output signal. For example, DLL control circuitry and DCC control circuitry may each adjust a delay of a variable delay line. The DLL control circuitry adjusts the delay such that an output clock signal is synchronized with an input clock signal. The DCC control circuitry detects a duty cycle error in the output clock signal and adjusts the delay of the variable delay line to achieve a duty cycle corrected output signal.Type: GrantFiled: March 25, 2008Date of Patent: September 13, 2011Assignee: Micron Technology, Inc.Inventors: Eric Becker, Eric Booth, Tyler Gomm
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Publication number: 20110204948Abstract: Duty cycle correction systems and methods of adjusting duty cycles are provided. One such duty cycle correction system includes a duty cycle adjustor and a variable delay line coupled to the output of the duty cycle adjustor. First and second phase detectors have first inputs coupled to the output of the duty cycle adjustor through an inverter and second inputs coupled to the output of the variable delay line. The phase detectors cause the delay line to align rising or falling edges of signals at the output of the delay line with rising or falling edges, respectively, of signals at the output of the inverter. The controller simultaneously causes the duty cycle adjustor to adjust the duty cycle of the output clock signal until the rising and falling edges of signals at the output of the delay line are aligned with rising and falling edges, respectively, of signals at the output of the inverter.Type: ApplicationFiled: April 29, 2011Publication date: August 25, 2011Applicant: Micron Technology, Inc.Inventors: YASUO SATOH, Eric Booth
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Publication number: 20110175655Abstract: A locked loop may have an adjustable hysteresis and/or a tracking speed that can be programmed by a user of an electronic device containing the locked loop or controlled by an integrated circuit device containing the locked loop during operation of the device. The looked loop may include a phase detector having a variable hysteresis, which may be coupled to receive a reference clock signal and an output clock signal from a phase adjustment circuit through respective frequency dividers that can vary the rate at which the phase detector compares the phase of the output clock signal to the phase of the reference clock signal, thus varying the tracking speed of the loop. The hysteresis and tracking speed of the locked loop may be programmed using a variety of means, such as by a temperature sensor for the electronic device, a mode register, a memory device command decoder, etc.Type: ApplicationFiled: March 29, 2011Publication date: July 21, 2011Applicant: Micron Technology, Inc.Inventors: Eric Booth, George G. Carey, Brian Callaway
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Publication number: 20110156788Abstract: The present disclosure is directed to a unit phase mixer in combination with an input buffer. The unit phase mixer has a pull-up path for pulling an output terminal up to a first voltage. The pull-up path has a first transistor responsive to a first enable signal and a series connected second transistor responsive to a first clock signal. The unit phase mixer has a pull-down path for pulling the output terminal down to a second voltage. The pull-down path has a third transistor responsive to a second clock signal and a series connected fourth transistor responsive to a second enable signal. The input buffer skews the first and second clock signals by different amounts to enable a break-before-make method of operation so that the first voltage is not connected to the second voltage. The unit phase mixer can be used as a building block in more complex mixers which may include the ability to weight the input clocks as well as providing feed-forward paths for certain of the signals.Type: ApplicationFiled: March 4, 2011Publication date: June 30, 2011Inventors: Chang-Ki Kwon, Eric Booth
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Publication number: 20110140759Abstract: Phase mixers, clock signal generators, memories and methods for providing an output signal having a phase relative to the phase difference of input clock signals are disclosed. One such phase mixer includes a phase mixer circuit having inputs and an output. The phase mixer is configured to receive a plurality of input clock signals and generate an output clock signal at the output having a phase relative to the plurality of input clock signals. The phase mixer further includes an adjustment circuit coupled to the phase mixer circuit. In some phase mixers, a control circuit coupled to the phase mixer circuit and the adjustment circuit is included. The control circuit is configured to generate a control signal based on the input signals to adjust an electrical load-to-drive ratio of the phase mixer.Type: ApplicationFiled: February 17, 2011Publication date: June 16, 2011Applicant: Micron Technology, Inc.Inventor: Eric Booth
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Patent number: 7940103Abstract: Duty cycle correction systems and methods of adjusting duty cycles are provided. One such duty cycle correction system includes a duty cycle adjustor and a variable delay line coupled to the output of the duty cycle adjustor. First and second phase detectors have first inputs coupled to the output of the duty cycle adjustor through an inverter and second inputs coupled to the output of the variable delay line. The phase detectors cause the delay line to align rising or falling edges of signals at the output of the delay line with rising or falling edges, respectively, of signals at the output of the inverter. The controller simultaneously causes the duty cycle adjustor to adjust the duty cycle of the output clock signal until the rising and falling edges of signals at the output of the delay line are aligned with rising and falling edges, respectively, of signals at the output of the inverter.Type: GrantFiled: March 9, 2009Date of Patent: May 10, 2011Assignee: Micron Technology, Inc.Inventors: Yasuo Satoh, Eric Booth
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Patent number: 7928782Abstract: A locked loop may have an adjustable hysteresis and/or a tracking speed that can be programmed by a user of an electronic device containing the locked loop or controlled by an integrated circuit device containing the locked loop during operation of the device. The looked loop may include a phase detector having a variable hysteresis, which may be coupled to receive a reference clock signal and an output clock signal from a phase adjustment circuit through respective frequency dividers that can vary the rate at which the phase detector compares the phase of the output clock signal to the phase of the reference clock signal, thus varying the tracking speed of the loop. The hysteresis and tracking speed of the locked loop may be programmed using a variety of means, such as by a temperature sensor for the electronic device, a mode register, a memory device command decoder, etc.Type: GrantFiled: January 28, 2009Date of Patent: April 19, 2011Assignee: Micron Technology, Inc.Inventors: Eric Booth, George G. Carey, Brian Callaway
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Patent number: 7907928Abstract: The present disclosure is directed to a unit phase mixer in combination with an input buffer. The unit phase mixer has a pull-up path for pulling an output terminal up to a first voltage. The pull-up path has a first transistor responsive to a first enable signal and a series connected second transistor responsive to a first clock signal. The unit phase mixer has a pull-down path for pulling the output terminal down to a second voltage. The pull-down path has a third transistor responsive to a second clock signal and a series connected fourth transistor responsive to a second enable signal. The input buffer skews the first and second clock signals by different amounts to enable a break-before-make method of operation so that the first voltage is not connected to the second voltage. The unit phase mixer can be used as a building block in more complex mixers which may include the ability to weight the input clocks as well as providing feed-forward paths for certain of the signals.Type: GrantFiled: November 7, 2007Date of Patent: March 15, 2011Assignee: Micron Technology, Inc.Inventors: Chang-Ki Kwon, Eric Booth
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Patent number: 7902896Abstract: Phase mixers, clock signal generators, memories and methods for providing an output signal having a phase relative to the phase difference of input clock signals are disclosed. One such phase mixer includes a phase mixer circuit having inputs and an output. The phase mixer is configured to receive a plurality of input clock signals and generate an output clock signal at the output having a phase relative to the plurality of input clock signals. The phase mixer further includes an adjustment circuit coupled to the phase mixer circuit. In some phase mixers, a control circuit coupled to the phase mixer circuit and the adjustment circuit is included. The control circuit is configured to generate a control signal based on the input signals to adjust an electrical load-to-drive ratio of the phase mixer.Type: GrantFiled: June 12, 2009Date of Patent: March 8, 2011Assignee: Micron Technology, Inc.Inventor: Eric Booth
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Publication number: 20100315147Abstract: Phase mixers, clock signal generators, memories and methods for providing an output signal having a phase relative to the phase difference of input clock signals are disclosed. One such phase mixer includes a phase mixer circuit having inputs and an output. The phase mixer is configured to receive a plurality of input clock signals and generate an output clock signal at the output having a phase relative to the plurality of input clock signals. The phase mixer further includes an adjustment circuit coupled to the phase mixer circuit. In some phase mixers, a control circuit coupled to the phase mixer circuit and the adjustment circuit is included. The control circuit is configured to generate a control signal based on the input signals to adjust an electrical load-to-drive ratio of the phase mixer.Type: ApplicationFiled: June 12, 2009Publication date: December 16, 2010Applicant: Micron Technology, Inc.Inventor: Eric Booth
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Publication number: 20100225372Abstract: Duty cycle correction systems and methods of adjusting duty cycles are provided. One such duty cycle correction system includes a duty cycle adjustor and a variable delay line coupled to the output of the duty cycle adjustor. First and second phase detectors have first inputs coupled to the output of the duty cycle adjustor through an inverter and second inputs coupled to the output of the variable delay line. The phase detectors cause the delay line to align rising or falling edges of signals at the output of the delay line with rising or falling edges, respectively, of signals at the output of the inverter. The controller simultaneously causes the duty cycle adjustor to adjust the duty cycle of the output clock signal until the rising and falling edges of signals at the output of the delay line are aligned with rising and falling edges, respectively, of signals at the output of the inverter.Type: ApplicationFiled: March 9, 2009Publication date: September 9, 2010Applicant: Micron Technology, Inc.Inventors: Yasuo Satoh, Eric Booth
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Publication number: 20100188125Abstract: A locked loop may have an adjustable hysteresis and/or a tracking speed that can be programmed by a user of an electronic device containing the locked loop or controlled by an integrated circuit device containing the locked loop during operation of the device. The looked loop may include a phase detector having a variable hysteresis, which may be coupled to receive a reference clock signal and an output clock signal from a phase adjustment circuit through respective frequency dividers that can vary the rate at which the phase detector compares the phase of the output clock signal to the phase of the reference clock signal, thus varying the tracking speed of the loop. The hysteresis and tracking speed of the locked loop may be programmed using a variety of means, such as by a temperature sensor for the electronic device, a mode register, a memory device command decoder, etc.Type: ApplicationFiled: January 28, 2009Publication date: July 29, 2010Inventors: ERIC BOOTH, George G. Carey, Brian Callaway
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Patent number: 7728639Abstract: Disclosed herein is improved delay locked loop (DLL) initialization circuitry that alters the measurement used to initialize the variable delay line's delay (e.g., entry point or exit point) by using three clock phases: the DLL reference clock (input to the delay line), the reference clock as trimmed by a delay Tref, and the feedback clock as trimmed by a delay Tfb. By using these three phases at the appropriate time, the measurement is aware of the Tac trim for both positive (Tref) and negative (Tfb) trims. Specifically, measurement ‘start’ and ‘stop’ signals each pass through only one of delays Tref and Tfb, such that error in the measurement is a function of both Tref and Tfb. This improves the accuracy of the measurement such that additional shifting of the DLL is not necessary after initialization, and allows a wide trim range even for high clock frequencies.Type: GrantFiled: October 8, 2008Date of Patent: June 1, 2010Assignee: Micron Technology, Inc.Inventors: Tyler Gomm, Eric Booth, Jongtae Kwak
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Publication number: 20090243677Abstract: Closed-loop duty-cycle correctors (DCCs), clock generators, memory devices, systems, and methods for generating an output clock signal having a particular duty cycle are provided, such as clock generators configured to generate an output clock signal synchronized with a received input clock signal having a predetermined duty cycle. Embodiments of clock generators include closed-loop duty cycle correctors that receive an already-controlled and corrected output signal. For example, DLL control circuitry and DCC control circuitry may each adjust a delay of a variable delay line. The DLL control circuitry adjusts the delay such that an output clock signal is synchronized with an input clock signal. The DCC control circuitry detects a duty cycle error in the output clock signal and adjusts the delay of the variable delay line to achieve a duty cycle corrected output signal.Type: ApplicationFiled: March 25, 2008Publication date: October 1, 2009Applicant: Micron Technology, Inc.Inventors: Eric Becker, Eric Booth, Tyler Gomm
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Publication number: 20090116602Abstract: The present disclosure is directed to a unit phase mixer in combination with an input buffer. The unit phase mixer has a pull-up path for pulling an output terminal up to a first voltage. The pull-up path has a first transistor responsive to a first enable signal and a series connected second transistor responsive to a first clock signal. The unit phase mixer has a pull-down path for pulling the output terminal down to a second voltage. The pull-down path has a third transistor responsive to a second clock signal and a series connected fourth transistor responsive to a second enable signal. The input buffer skews the first and second clock signals by different amounts to enable a break-before-make method of operation so that the first voltage is not connected to the second voltage. The unit phase mixer can be used as a building block in more complex mixers which may include the ability to weight the input clocks as well as providing feed-forward paths for certain of the signals.Type: ApplicationFiled: November 7, 2007Publication date: May 7, 2009Inventors: Chang-Ki Kwon, Eric Booth
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Publication number: 20090027094Abstract: Disclosed herein is improved delay locked loop (DLL) initialization circuitry that alters the measurement used to initialize the variable delay line's delay (e.g., entry point or exit point) by using three clock phases: the DLL reference clock (input to the delay line), the reference clock as trimmed by a delay Tref, and the feedback clock as trimmed by a delay Tfb. By using these three phases at the appropriate time, the measurement is aware of the Tac trim for both positive (Tref) and negative (Tfb) trims. Specifically, measurement ‘start’ and ‘stop’ signals each pass through only one of delays Tref and Tfb, such that error in the measurement is a function of both Tref and Tfb. This improves the accuracy of the measurement such that additional shifting of the DLL is not necessary after initialization, and allows a wide trim range even for high clock frequencies.Type: ApplicationFiled: October 8, 2008Publication date: January 29, 2009Applicant: MICRON TECHNOLOGY, INC.Inventors: Tyler Gomm, Eric Booth, Jongtae Kwak
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Patent number: 7443216Abstract: Disclosed herein is improved delay locked loop (DLL) initialization circuitry that alters the measurement used to initialize the variable delay line's delay (e.g., entry point or exit point) by using three clock phases: the DLL reference clock (input to the delay line), the reference clock as trimmed by a delay Tref, and the feedback clock as trimmed by a delay Tfb. By using these three phases at the appropriate time, the measurement is aware of the Tac trim for both positive (Tref) and negative (Tfb) trims. Specifically, measurement ‘start’ and ‘stop’ signals each pass through only one of delays Tref and Tfb, such that error in the measurement is a function of both Tref and Tfb. This improves the accuracy of the measurement such that additional shifting of the DLL is not necessary after initialization, and allows a wide trim range even for high clock frequencies.Type: GrantFiled: February 20, 2007Date of Patent: October 28, 2008Assignee: Micron Technology, Inc.Inventors: Tyler Gomm, Eric Booth, Jongtae Kwak
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Publication number: 20080197899Abstract: Disclosed herein is improved delay locked loop (DLL) initialization circuitry that alters the measurement used to initialize the variable delay line's delay (e.g., entry point or exit point) by using three clock phases: the DLL reference clock (input to the delay line), the reference clock as trimmed by a delay Tref, and the feedback clock as trimmed by a delay Tfb. By using these three phases at the appropriate time, the measurement is aware of the Tac trim for both positive (Tref) and negative (Tfb) trims. Specifically, measurement ‘start’ and ‘stop’ signals each pass through only one of delays Tref and Tfb, such that error in the measurement is a function of both Tref and Tfb. This improves the accuracy of the measurement such that additional shifting of the DLL is not necessary after initialization, and allows a wide trim range even for high clock frequencies.Type: ApplicationFiled: February 20, 2007Publication date: August 21, 2008Applicant: Micron Technology, Inc.Inventors: Tyler Gomm, Eric Booth, Jongtae Kwak
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Patent number: 7347052Abstract: Methods and systems for processing uncalcined coke are provided. The methods and systems provide for combusting effluent gas from a refinery unit and a stream of uncalcined coke. The refinery unit effluent gas may be the offgas from a rotary kiln calciner. The refinery unit effluent gas and the uncalcined coke stream are combusted in an integrated gas/solids incinerator. Heat released during the combustion of these streams may be used to generate steam or electricity. The methods and systems disclosed provide low cost energy production at calciner effluent gas incinerator locations where uncalcined coke is available.Type: GrantFiled: January 12, 2004Date of Patent: March 25, 2008Assignee: Conocophillips CompanyInventors: Todd W. Dixon, Dennis A. Smith, Carl L. Williams, Eric Booth
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Patent number: D642846Type: GrantFiled: March 2, 2010Date of Patent: August 9, 2011Assignee: Smirthwaite LimitedInventors: Simon Mark Parish, Pauline Pope, Eric Booth