Abstract: Full-wafer inspection methods for a semiconductor wafer are disclosed. One method includes making a measurement of a select measurement parameter simultaneously over measurement sites of the entire surface of the semiconductor wafer at a maximum measurement-site pixel density ?max to obtain measurement data, wherein the total number of measurement-site pixels obtained at the maximum measurement-site pixel density ?max is between 104 and 108. The method also includes defining a plurality of zones of the surface of the semiconductor wafer, with each of the zones having a measurement-site pixel density ?, with at least two of the zones having a different sized measurement-site pixel and thus a different measurement-site pixel density ?. The method also includes processing the measurement data based on the plurality of zones and the corresponding measurement-site pixel densities ?.

Abstract: A metrology recipe includes dynamic instructions that allow a metrology tool to perform a secondary metrology operation on a test wafer when previous measurement data indicates a process issue with that test wafer. The metrology recipe can instruct the metrology tool to perform an efficient default metrology operation on all test wafers, and perform a more in-depth secondary metrology operation on only those wafers that warrant additional scrutiny. In this manner, critical metrology data can be captured with a minimum of effect on metrology throughput. The metrology data used to determine whether or not the secondary metrology operation is to be performed can be generated from default metrology operations within the same tool, or can be generated by measurements taken by a completely different tool. Such “external” metrology data can be received via a communications network, either directly or from a server on the network for processing the metrology data.

Abstract: A method for measuring three-dimensional gate dielectric structures can involve forming test patterns that cover a range of dimensional values for the fins on which the gate dielectric structures are formed. Then, by measuring the gate dielectric properties and then correlating those measurements with the underlying fin dimensions, a relationship between fin dimension(s) and gate dielectric properties can be determined. That relationship can then be applied to actual device structures to interpolate/extrapolate gate dielectric property values based on the fin dimensions in the actual device.

Abstract: A reticle 100 includes two or more image patterns for different layers of an integrated circuit, each one in a separate image field 110-120. These image layers are used in the production of the same integrated circuit. By placing multiple image layers on the same reticle, fewer reticles need to be produced and a prototype circuit can then be made more cheaply. Likewise the reduced set of reticles can be used where there is a limited run of circuits. If any or all reticle layers need to be replaced, then the replacement set is also cheaper.