Patents by Inventor Eric Bouyoux

Eric Bouyoux has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6779105
    Abstract: The present invention relates to a pipeline microprocessor (MP) comprising a first pipeline stage (ST1) comprising means IPC, MMU, PC, B2, DEC1) for reading and decoding instructions (CODEOP, ADRs, ADRd) of a program recorded in a memory (MEM), and a second pipeline stage (ST2), contiguous to the first pipeline stage, comprising two sectors (ST21, ST22) activated one after the other during complementary half-cycles of a clock signal (H1) of the microprocessor. The first sector reads data contained in two registers (Rd, Rs) of a bank of registers (BANK1, BANK2) of the microprocessor and carries out an operation on the data according to an instruction (CODEOP, ADRs, ADRd) received at the previous clock cycle. The second sector (ST22) comprises means (B4, DEC1) to record the result of the operation in a register of the bank of registers (BANK1, BANK2). Application especially to chip cards.
    Type: Grant
    Filed: May 3, 2000
    Date of Patent: August 17, 2004
    Assignee: Inside Technologies
    Inventors: Eric Bouyoux, Bruno Charrat, Nicolas Pangaud, Sean Commercial
  • Patent number: 6678819
    Abstract: The present invention relates to a pipeline microprocessor (MP1, MP2) comprising a program counter (PC), means (MUX, ADD) for the incrementation of the program counter (PC), instruction decoding means (PREDEC, DEC1, DEC2, DEC3) comprising means (PREDEC) to decode a conditional jump instruction (JMPc) of the program counter, a bank of registers (REGBANK), a computation unit (ALU) comprising a first output (S1) to deliver a result and a second output (S2) to deliver status bits (C, N, P, Z) of the result. According to the invention, the computation unit (ALU) and the means (PREDEC, DEC3) for decoding the conditional jump instruction (JMPc) are laid out in two neighboring pipeline stages (ST1, ST2), and the means (PREDEC) for decoding the conditional jump instruction (JMPc) are connected to the second output (S2) of the computation unit (ALU).
    Type: Grant
    Filed: May 3, 2000
    Date of Patent: January 13, 2004
    Assignee: Inside Technologies
    Inventor: Eric Bouyoux
  • Patent number: 6337619
    Abstract: A method for selecting an electronic module from a plurality of at least two modules (M1, M2, M3) capable of emitting messages simultaneously, includes the steps of sending a general query message (ACTIVALL) to the modules, and selecting (AFI, SELECT-ID) the module having responded first, the modules, on receiving a query message (ACTIVALL, ACTIV), determining a random time interval (P) and sending a responding message (ID, R) when the said time interval (P) has elapsed. A module is set in idle position (IDL) when it receives a message (MESS) before the time interval (P) preceding the sending of a response (ID, R) has elapsed. The idle position (IDL) is at least characterized by the fact that one module does not respond, subsequently, to a complementary query message (ACTIV). This invention is particularly useful for contactless smart card readers and for terminals for electronic labels.
    Type: Grant
    Filed: November 6, 1998
    Date of Patent: January 8, 2002
    Assignee: Inside Technologies
    Inventors: Jacek Kowalski, Bruno Charrat, Eric Bouyoux, Michel Martin