Abstract: A macro cell includes one or more vertical die interconnects that vertically span the macro cell to transmit a data signal. The macro cell also includes one or more isolation features configured to manage a power of the macro cell by controlling a transmission of the data signal. Additionally, the macro cell includes one or more flip-flops configured to control a timing of the transmission of the data signal through the one or more vertical die interconnects. Various other apparatuses and systems are also disclosed.

Abstract: A macro cell includes one or more vertical die interconnects that vertically span the macro cell to transmit a data signal. The macro cell also includes one or more isolation features configured to manage a power of the macro cell by controlling a transmission of the data signal. Additionally, the macro cell includes one or more flip-flops configured to control a timing of the transmission of the data signal through the one or more vertical die interconnects. Various other apparatuses and systems are also disclosed.

Abstract: An integrated circuit die includes a set of electronic circuits disposed on a semiconductor material. The integrated circuit die also includes one or more through-silicon vias that vertically span the semiconductor material to transmit data signals. Additionally, the integrated circuit die includes a programmable delay element integrated with the set of electronic circuits on the semiconductor material and configured to delay data signals. Various other apparatuses, systems, and methods are also disclosed.

Abstract: A bonded die assembly includes first conductive pads of a first substrate each bonded to respective second conductive pads of a second substrate, the first and second conductive pads arrayed at an inter-pad spacing, a plurality of active components located in the second substrate and arrayed at an inter-component spacing, and a metallization structure disposed between the first substrate and the second substrate, where the metallization structure is configured to decrease the inter-component spacing relative to the inter-pad spacing. The die assembly is characterized by an improved utilization of available device active area.

Abstract: A method for controlling power in 3D stacked die can include configuring a first die of a set of 3D stacked die to receive power from a power source, wherein the first die includes one or more field effect transistors configured to control the power. The method can also include configuring one or more power domains included in a second die of the set of 3D stacked die to receive the power that is controlled by the one or more field effect transistors included in the first die. Various other methods and systems are also disclosed.

Abstract: An integrated circuit includes one or more processing units that execute instructions that employ a register file, control logic creates a pre-startup register free list, prior to normal operation of at least one of the processing units, that includes a list of registers devoid of defective registers. In some implementations, no column and row repair information is provided to register file repair logic. In certain examples, the register file is configured as a repair-less register file. During normal operation of the one or more processing units, the integrated circuit employs the pre-startup register free list to select registers in a register file for the executing instructions. Associated methods are also presented.

Abstract: An integrated circuit includes one or more processing units that execute instructions that employ a register file, control logic creates a pre-startup register free list, prior to normal operation of at least one of the processing units, that includes a list of registers devoid of undefective registers. In some implementations, no column and row repair information is provided to register file repair logic. In certain examples, the register file is configured as a repair-less register file. During normal operation of the one or more processing units, the integrated circuit employs the pre-startup register free list to select registers in a register file for the executing instructions. Associated methods are also presented.

Abstract: A processing system reduces by staging precharging of bitlines of a memory. In a static random access memory (SRAM) array, the voltage level on every bitline in the array is precharged to a reference voltage (VDD) rail voltage before a memory access. To facilitate reduction of current spikes from precharging, a precharge control unit groups entries of a RAM into a plurality of subsets, or regions, and applies a different precharge signal for precharging bitlines associated with each subset. Application of the precharge signals to the respective subsets over time results in smaller current spikes than simultaneous application of precharge signals to all of the bitlines.

Abstract: A processing system reduces by staging precharging of bitlines of a memory. In a static random access memory (SRAM) array, the voltage level on every bitline in the array is precharged to a reference voltage (VDD) rail voltage before a memory access. To facilitate reduction of current spikes from precharging, a precharge control unit groups entries of a RAM into a plurality of subsets, or regions, and applies a different precharge signal for precharging bitlines associated with each subset. Application of the precharge signals to the respective subsets over time results in smaller current spikes than simultaneous application of precharge signals to all of the bitlines.

Abstract: A processing system includes a shadow tag memory, which stores a plurality of entries containing coherency information for the cachelines residing at the various levels of private caches. If a cache miss occurs at a private cache, or if coherency information for a cacheline requires updating, a probe is sent to the shadow tag memory maintained at the shared cache to determine whether the requested (or affected) cacheline is stored at another private cache. The probe includes a tag which can be divided into two or more portions. To more efficiently compare the probe tag to the shadow tag entries, the comparison is performed in multiple stages based on the portions of the probe tag.

Abstract: A processing system includes a shadow tag memory, which stores a plurality of entries containing coherency information for the cachelines residing at the various levels of private caches. If a cache miss occurs at a private cache, or if coherency information for a cacheline requires updating, a probe is sent to the shadow tag memory maintained at the shared cache to determine whether the requested (or affected) cacheline is stored at another private cache. The probe includes a tag which can be divided into two or more portions. To more efficiently compare the probe tag to the shadow tag entries, the comparison is performed in multiple stages based on the portions of the probe tag.