Patents by Inventor Eric C. Cota-Robles

Eric C. Cota-Robles has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Invalidating translation lookaside buffer entries in a virtual machine system
    Patent number: 8751752
    Abstract: One embodiment of the present invention is a technique to invalidate entries in a translation lookaside buffer (TLB). A TLB in a processor has a plurality of TLB entries. Each TLB entry is associated with a virtual machine extension (VMX) tag word indicating if the associated TLB entry is invalidated according to a processor mode when an invalidation operation is performed. The processor mode is one of execution in a virtual machine (VM) and execution not in a virtual machine.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: June 10, 2014
    Assignee: Intel Corporation
    Inventors: Eric C. Cota-Robles, Stalinselvaraj Jeyasingh, Alain Kagi, Michael A. Kozuch, Gilbert Neiger, Richard Uhlig
  • Invalidating translation lookaside buffer entries in a virtual machine (VM) system
    Patent number: 8543772
    Abstract: One embodiment of the present invention is a technique to invalidate entries in a translation lookaside buffer (TLB). A TLB in a processor has a plurality of TLB entries. Each TLB entry is associated with a virtual machine extension (VMX) tag word indicating if the associated TLB entry is invalidated according to a processor mode when an invalidation operation is performed. The processor mode is one of execution in a virtual machine (VM) and execution not in a virtual machine.
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: September 24, 2013
    Assignee: Intel Corporation
    Inventors: Eric C. Cota-Robles, Andy Glew, Stalinselvaraj Jeyasingh, Alain Kagi, Michael A. Kozuch, Gilbert Neiger, Richard Uhlig
  • INVALIDATING TRANSLATION LOOKASIDE BUFFER ENTRIES IN A VIRTUAL MACHINE SYSTEM
    Publication number: 20130212313
    Abstract: One embodiment of the present invention is a technique to invalidate entries in a translation lookaside buffer (TLB). A TLB in a processor has a plurality of TLB entries. Each TLB entry is associated with a virtual machine extension (VMX) tag word indicating if the associated TLB entry is invalidated according to a processor mode when an invalidation operation is performed. The processor mode is one of execution in a virtual machine (VM) and execution not in a virtual machine.
    Type: Application
    Filed: March 15, 2013
    Publication date: August 15, 2013
    Inventors: Eric C. Cota-Robles, Andy Glew, Stalinselvaraj Jeyasingh, Alain Kagi, Michael A. Kozuch, Gilbert Neiger, Richard Uhlig