Abstract: A sensor includes control circuitry and a pixel having a photo site, a first storage node and a second storage node. The control circuitry operates to transfer a first collected signal produced by light from a first image from the photo site to the first storage node during a first period, to transfer a second collected signal produced by light from a second image from the photo site to the second storage node during a second period that follows the first period and to transfer the first and second collected signals out of the pixel during a third period that follows the second period. The first storage node includes a first capacitor and a first reset gate coupled directly between the first capacitor and a reset voltage. The second storage node includes a second capacitor and a second reset gate coupled directly between the second capacitor and the reset voltage.

Abstract: A sensor includes control circuitry and a pixel. The pixel includes a photo site, a first storage node and a second storage node. The control circuitry causes the pixel to transfer a first collected signal from the photo site to the first storage node during a first period, to transfer a second collected signal from the photo site to the second storage node during a second period that follows the first period, and to transfer the first and second collected signals out of the pixel during a third period that follows the second period.

Abstract: A sensor formed in a substrate of a first conductivity type in a first concentration to express a first intrinsic potential includes CMOS circuitry to control the sensor, a first well of the first conductivity type in a second concentration (greater than the first concentration) formed in the substrate to express a second intrinsic potential, and a photodiode region of a second conductivity type formed in the first well. The first and second intrinsic potentials induce a field between the substrate and the first well that repels photo generated charge from drifting from the substrate into the first well. Alternatively, a sensor formed in a substrate of a first conductivity type includes CMOS circuitry to control the sensor, a first well of a second conductivity type formed in the substrate, a second well of the first conductivity type formed in the first well, and a photodiode region of the second conductivity type formed in the second well.

Abstract: A method of using a pinned photodiode pixel for high-speed motion-capture CMOS image sensors uses a pinned photodiode in a five-transistor pixel so that the channel region of the photodiode is completely voided of charge after reset and readout operations. An exemplary method includes applying an exposure control clock signal to a gate electrode of an exposure control transistor of a five-transistor pixel, applying a pixel preset voltage to a drain of the exposure control transistor, and switching the exposure control clock signal. The exposure control transistor is coupled between a pinned photodiode of the pixel and the pixel preset voltage. The switching the exposure control clock signal turns off the exposure control transistor at a beginning of an integration cycle after substantially all signal charge has drained out of the pinned photodiode and across the exposure control transistor so that the pinned photodiode is fully voided of majority carriers.

Abstract: A pixel includes five transistors, a pinned photodiode and a storage node. A first transistor is coupled between the pinned photodiode and the storage node. A second transistor is coupled between the storage node and an output drain voltage. A third transistor is coupled between the pinned photodiode and a pixel reset voltage. The pixel reset voltage is different than the output drain voltage.

Abstract: A pixel includes a photon detecting element coupled between a node and a ground, a transistor structure coupled between the node and a first predetermined voltage to provide a logarithmic response region, and a reset transistor coupled between the node and a second predetermined voltage to provide a linear response region where the second predetermined voltage is greater than the first predetermined voltage.