Patents by Inventor Eric C. Fromm
Eric C. Fromm has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10944694Abstract: This patent application relates generally to a predictive arbitration circuit for use in arbitrating access by a number of data streams to a shared resource managed by a destination (arbiter), where each data stream is associated with a number of sources competing for the shared resource, and the destination provides access to the shared resource based on the number of sources competing for the shared resource rather than just on the number of data streams. Among other things, this approach can more fairly distribute access to the shared resource among the competing sources.Type: GrantFiled: December 6, 2016Date of Patent: March 9, 2021Assignee: Hewlett Packard Enterprise Development LPInventors: Joseph G. Tietz, Eric C. Fromm
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Patent number: 10721185Abstract: This patent application relates generally to an age-based arbitration circuit for use in arbitrating access by a number of data streams to a shared resource managed by a destination (arbiter), in which age-based determinations are performed at the input sources of the data streams in order to designate certain packets as high-priority packets based on packet ages, and the destination expedites processing of the high-priority packets. Among other things, this approach offloads the age-based determinations from the destination, where they otherwise can cause delays in processing packets.Type: GrantFiled: December 6, 2016Date of Patent: July 21, 2020Assignee: Hewlett Packard Enterprise Development LPInventors: Joseph G. Tietz, Eric C. Fromm
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Patent number: 10592465Abstract: A node controller for a first processor socket group may include a node memory storing a coherence directory and logic. Logic may cause the node controller to: receive a memory operation request directly from a second processor socket group, follow a coherence protocol based on the memory operation request and the coherence directory and directly access a socket group memory of the first processor socket group based on the request.Type: GrantFiled: October 26, 2017Date of Patent: March 17, 2020Assignee: Hewlett Packard Enterprise Development LPInventors: Frank R. Dropps, Eric C. Fromm
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Patent number: 10521260Abstract: A high performance computing (HPC) system has an architecture that separates data paths used by compute nodes exchanging computational data from the data paths used by compute nodes to obtain computational work units and save completed computations. The system enables an improved method of saving checkpoint data, and an improved method of using an analysis of the saved data to assign particular computational work units to particular compute nodes. The system includes a compute fabric and compute nodes that cooperatively perform a computation by mutual communication using the compute fabric. The system also includes a local data fabric that is coupled to the compute nodes, a memory, and a data node. The data node is configured to retrieve data for the computation from an external bulk data storage, and to store its work units in the memory for access by the compute nodes.Type: GrantFiled: July 14, 2017Date of Patent: December 31, 2019Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LPInventors: Steven J. Dean, Michael Woodacre, Randal S. Passint, Eric C. Fromm, Thomas E. McGee, Michael E. Malewicki, Kirill Malkin
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Publication number: 20190129884Abstract: A node controller for a first processor socket group may include a node memory storing a coherence directory and logic. Logic may cause the node controller to: receive a memory operation request directly from a second processor socket group, follow a coherence protocol based on the memory operation request and the coherence directory and directly access a socket group memory of the first processor socket group based on the request.Type: ApplicationFiled: October 26, 2017Publication date: May 2, 2019Inventors: Frank R. Dropps, Eric C. Fromm
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Publication number: 20180159800Abstract: This patent application relates generally to an age-based arbitration circuit for use in arbitrating access by a number of data streams to a shared resource managed by a destination (arbiter), in which age-based determinations are performed at the input sources of the data streams in order to designate certain packets as high-priority packets based on packet ages, and the destination expedites processing of the high-priority packets. Among other things, this approach offloads the age-based determinations from the destination, where they otherwise can cause delays in processing packets.Type: ApplicationFiled: December 6, 2016Publication date: June 7, 2018Inventors: Joseph G. Tietz, Eric C. Fromm
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Publication number: 20180159799Abstract: This patent application relates generally to a predictive arbitration circuit for use in arbitrating access by a number of data streams to a shared resource managed by a destination (arbiter), where each data stream is associated with a number of sources competing for the shared resource, and the destination provides access to the shared resource based on the number of sources competing for the shared resource rather than just on the number of data streams. Among other things, this approach can more fairly distribute access to the shared resource among the competing sources.Type: ApplicationFiled: December 6, 2016Publication date: June 7, 2018Inventors: Joseph G. Tietz, Eric C. Fromm
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Publication number: 20180018196Abstract: A high performance computing (HPC) system has an architecture that separates data paths used by compute nodes exchanging computational data from the data paths used by compute nodes to obtain computational work units and save completed computations. The system enables an improved method of saving checkpoint data, and an improved method of using an analysis of the saved data to assign particular computational work units to particular compute nodes. The system includes a compute fabric and compute nodes that cooperatively perform a computation by mutual communication using the compute fabric. The system also includes a local data fabric that is coupled to the compute nodes, a memory, and a data node. The data node is configured to retrieve data for the computation from an external bulk data storage, and to store its work units in the memory for access by the compute nodes.Type: ApplicationFiled: July 14, 2017Publication date: January 18, 2018Inventors: Steven J. Dean, Michael Woodacre, Randal S. Passint, Eric C. Fromm, Thomas E. McGee, Michael E. Malewicki, Kirill Malkin
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Patent number: 9237093Abstract: An adaptive router anticipates possible future congestion and enables selection of an alternative route before the congestion occurs, thereby avoiding the congestion. The adaptive router may use a primary route until it predicts congestion will occur. The adaptive router measures packet traffic volume, such as flit volume, on a primary network interface to anticipate the congestion. The adaptive router maintains a trailing sum of the number of flits handled by the primary network interface over a trailing time period. If the sum exceeds a threshold value, the adaptive router assumes the route will become congested, and the adaptive router enables considering routing future packets, or at least the current packet, over possible secondary routes.Type: GrantFiled: March 14, 2013Date of Patent: January 12, 2016Assignee: Silicon Graphics International Corp.Inventors: Joseph George Tietz, Gregory Michael Thorson, Eric C. Fromm
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Patent number: 9104343Abstract: Processor clock signals are generated for each processor in a HPC system, such that all the processor clock signals are of the same frequency. Furthermore, as part of a startup (boot) procedure, a process sets all time stamp counters (TSCs) of the processors, such they indicate identical times. Each blade of the HPC system recovers a recovered clock signal from a synchronous communication network, to which the blade is coupled. The blade generates a processor clock from the recovered clock signal and provides the processor clock to processor(s) on the blade. Each chassis is coupled to a second, system-wide, synchronous communication network, and each chassis synchronizes its chassis synchronous communication network with the system-wide synchronous communication system. Thus, all the processor clock signals are generated with the same frequency.Type: GrantFiled: March 13, 2013Date of Patent: August 11, 2015Assignee: Silicon Graphics International Corp.Inventors: Rodney A. Ruesch, Eric C. Fromm, Robert W. Cutler, Richard G. Finstad, Dale R. Purdy, Brian J. Johnson, John F. Steiner
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Publication number: 20140281656Abstract: Processor clock signals are generated for each processor in a HPC system, such that all the processor clock signals are of the same frequency. Furthermore, as part of a startup (boot) procedure, a process sets all time stamp counters (TSCs) of the processors, such they indicate identical times. Each blade of the HPC system recovers a recovered clock signal from a synchronous communication network, to which the blade is coupled. The blade generates a processor clock from the recovered clock signal and provides the processor clock to processor(s) on the blade. Each chassis is coupled to a second, system-wide, synchronous communication network, and each chassis synchronizes its chassis synchronous communication network with the system-wide synchronous communication system. Thus, all the processor clock signals are generated with the same frequency.Type: ApplicationFiled: March 13, 2013Publication date: September 18, 2014Applicant: Silicon Graphics International Corp.Inventors: Rodney A. Ruesch, Eric C. Fromm, Robert W. Cutler, Richard G. Finstad, Dale R. Purdy, Brian J. Johnson, John F. Steiner
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Publication number: 20140281208Abstract: An associative look-up instruction for an instruction set architecture (ISA) of a processor and methods for use of an associative look-up instruction. The associative look-up instruction of the ISA specifies one or more fields within a data unit that are used as a pattern of bits for identifying data content in a memory structure to be loaded into hardware registers or other storage components of the ISA. Specified parameters of the associative operation may be explicit within the instruction or indirectly pointed to via hardware registers or other storage components of the ISA. The memory structure may be content addressable memory (CAM).Type: ApplicationFiled: March 13, 2013Publication date: September 18, 2014Applicant: SILICON GRAPHICS INTERNATIONAL CORP.Inventor: Eric C. Fromm
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Publication number: 20140269324Abstract: An adaptive router anticipates possible future congestion and enables selection of an alternative route before the congestion occurs, thereby avoiding the congestion. The adaptive router may use a primary route until it predicts congestion will occur. The adaptive router measures packet traffic volume, such as flit volume, on a primary network interface to anticipate the congestion. The adaptive router maintains a trailing sum of the number of flits handled by the primary network interface over a trailing time period. If the sum exceeds a threshold value, the adaptive router assumes the route will become congested, and the adaptive router enables considering routing future packets, or at least the current packet, over possible secondary routes.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Applicant: SILICON GRAPHICS INTERNATIONAL CORP.Inventors: Joseph George Tietz, Gregory Michael Thorson, Eric C. Fromm
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Publication number: 20140250252Abstract: A modular first-in first-out circuit including at least three non-addressable memory blocks forming a data pipeline is disclosed. At least two of the memory block including a data storage structure for receiving as input data from a global data bus and a control logic structure including logic for determining whether data should be added to the data storage structure from the global data bus and whether any data within the data storage structure should be transferred to the output of the memory block. The data storage structure of the at least two memory blocks includes a first data input for selectively receiving data from the global data bus and a second data input for selectively receiving data from a previous memory block in the modular first-in first-out circuit.Type: ApplicationFiled: March 4, 2013Publication date: September 4, 2014Applicant: SILICON GRAPHICS INTERNATIONAL CORP.Inventor: Eric C. Fromm
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Patent number: 8239566Abstract: Processing transaction requests in a shared memory multi-processor computer network is described. A transaction request is received at a servicing agent from a requesting agent. The transaction request includes a request priority associated with a transaction urgency generated by the requesting agent. The servicing agent provides an assigned priority to the transaction request based on the request priority, and then compares the assigned priority to an existing service level at the servicing agent to determine whether to complete or reject the transaction request. A reply message from the servicing agent to the requesting agent is generated to indicate whether the transaction request was completed or rejected, and to provide reply fairness state data for rejected transaction requests.Type: GrantFiled: February 28, 2008Date of Patent: August 7, 2012Assignee: Silicon Graphics International, Corp.Inventors: Eric C. Fromm, Gregory M. Thorson
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Patent number: 7587305Abstract: A method includes specifying a first set of interconnected devices associated with a first leaf cell in Verilog syntax, and specifying a second set of interconnected devices associated with a second leaf cell in Verilog syntax. A connection between the first leaf cell and the second leaf cell is also specified in Verilog syntax. This specifies a circuit. The functionality of the logic can be tested by running a logic simulation on the circuit without converting to Verilog syntax. The Verilog syntax, associated with the circuit, can be converted directly from Verilog syntax to a SPICE netlist. The SPICE netlist can be used to simulate the timing and other parameters of the circuit. The Verilog syntax can be used to verify the circuit. Also included are a computer readable medium including an instruction set for the above method, and a data structure necessary to carry out the above method.Type: GrantFiled: June 26, 2002Date of Patent: September 8, 2009Assignee: Cray Inc.Inventors: Robert J. Lutz, Mark S. Birrittella, Eric C. Fromm, Harro Zimmermann
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Publication number: 20090222821Abstract: Processing transaction requests in a shared memory multi-processor computer network is described. A transaction request is received at a servicing agent from a requesting agent. The transaction request includes a request priority associated with a transaction urgency generated by the requesting agent. The servicing agent provides an assigned priority to the transaction request based on the request priority, and then compares the assigned priority to an existing service level at the servicing agent to determine whether to complete or reject the transaction request. A reply message from the servicing agent to the requesting agent is generated to indicate whether the transaction request was completed or rejected, and to provide reply fairness state data for rejected transaction requests.Type: ApplicationFiled: February 28, 2008Publication date: September 3, 2009Applicant: SILICON GRAPHICS, INC.Inventors: Eric C. Fromm, Gregory M. Thorson
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Patent number: 6925547Abstract: A method of performing remote address translation in a multiprocessor system includes determining a connection descriptor and a virtual address at a local node, accessing a local connection table at the local node using the connection descriptor to produce a system node identifier for a remote node and a remote address space number, communicating the virtual address and remote address space number to the remote node, and translating the virtual address to a physical address at the remote node (qualified by the remote address space number). A user process running at the local node provides the connection descriptor and virtual address. The translation is performed by matching the virtual address and remote address space number with an entry of a translation-lookaside buffer (TLB) at the remote node. Performing the translation at the remote node reduces the amount of translation information needed at the local node for remote memory accesses.Type: GrantFiled: December 14, 2001Date of Patent: August 2, 2005Assignee: Silicon Graphics, Inc.Inventors: Steven L. Scott, Chris Dickson, Eric C. Fromm, Michael L. Anderson
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Patent number: 6839856Abstract: A bus interface circuit and method for reliable data capture in the presence of bus-master changeovers and/or for synchronizing received data to an internal clock signal, wherein the received data includes a strobe. Since the strobe may have a delay that is unknown (due to varying distances from the driver, clock jitter, and/or other causes), it is important to re-synchronize to the internal clock, and to do so with the smallest delay possible. This synchronization is provided in a way that also eliminates potential problems due to bus-master changeover, and in a way that minimizes time-critical signal generation. One aspect provides a method and/or apparatus for reliable data capture.Type: GrantFiled: July 20, 2000Date of Patent: January 4, 2005Assignee: Silicon Graphics, Inc.Inventors: Eric C. Fromm, Rodney Ruesch
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Patent number: 6779072Abstract: A method and apparatus for accessing memory-mapped registers that are distributed across a large integrated circuit. Some embodiments provide a method for accessing memory-mapped registers that are distributed across a first integrated circuit, the first integrated circuit including a plurality of logic subset modules, wherein each of the plurality of logic subset modules includes one or more memory-mapped registers. This method includes receiving a memory-mapped register access request into the first integrated circuit, serially transmitting, through each of the plurality of logic subset modules, a first plurality of data packets based on the memory-mapped register access request, wherein the first plurality of data packets includes an address specification for a memory-mapped register associated with a first one of the logic subset modules, and within the first logic subset module, accessing the memory-mapped register associated with the first logic subset module.Type: GrantFiled: July 20, 2000Date of Patent: August 17, 2004Assignee: Silicon Graphics, Inc.Inventors: Mark F. Sauder, Michael L. Anderson, Eric C. Fromm